MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 604
![IC MCU 16BIT 2K FLASH 112-LQFP](/photos/12/21/122158/mc9s12hz128val_sml.jpg)
MC9S12HZ128VAL
Manufacturer Part Number
MC9S12HZ128VAL
Description
IC MCU 16BIT 2K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ128VAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12HZ128VAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12HZ128VAL
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 22 Module Mapping Control (MMCV4)
22.1.1
22.1.2
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide,
special single chip, etc.). This is best understood from the register descriptions.
22.2
All interfacing with the MMC sub-block is done within the core, it has no external signals.
22.3
A summary of the registers associated with the MMC sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
22.3.1
604
•
•
•
•
•
•
•
•
•
•
•
Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM)
memory blocks and associated registers
Memory mapping control and selection based upon address decode and system operating mode
Core address bus control
Core data bus control and multiplexing
Core security state decoding
Emulation chip select signal generation (ECS)
External chip select signal generation (XCS)
Internal memory expansion
External stretch and ROM mapping control functions via the MISC register
Reserved registers for test purposes
Configurable system memory options defined at integration of core into the system-on-a-chip
(SoC).
External Signal Description
Memory Map and Register Definition
Address
Offset
Features
Modes of Operation
Module Memory Map
.
.
Initialization of Internal RAM Position Register (INITRM)
Initialization of Internal Registers Position Register (INITRG)
Initialization of Internal EEPROM Position Register (INITEE)
Miscellaneous System Control Register (MISC)
Reserved
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 22-1. MMC Memory Map
Register
.
.
Figure
22-2. Detailed
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
—
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