DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 18
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 1 CPU
Note: * The maximum operating frequency and instruction execution time differ depending on
1.1.2
Differences between the H8S/2600 CPU and the H8S/2000 CPU are as follows.
In addition, there may be defferences in address spaces, EXR register functions, power-down
states, and so on. For details, refer to the relevant microcontroller hardware manual.
Rev. 4.00 Feb 24, 2006 page 2 of 322
REJ09B0139-0400
High-speed operation
Two CPU operating modes
Power-down modes
Register configuration
Basic instructions
Number of states required for execution
All frequently-used instructions execute in one or two states
Maximum clock frequency:
8/16/32-bit register-register add/subtract: 50 ns
8
16
16
32
Normal mode
Advanced mode
Transition to power-down state by SLEEP instruction
CPU clock speed selection
The MAC register is supported only by the H8S/2600 CPU.
For details, see section 1.4, Register Configuration.
The MAC, CLRMAC, LDMAC, and STMAC instructions are supported only by the
H8S/2600 CPU.
For details, see section 1.6, Instruction Set, and Section 2, Instruction Descriptions.
The number of states required for execution of the MULXU and MULXS instructions.
For details, see section 2.6, Number of States Required for Execution.
Differences between H8S/2600 CPU and H8S/2000 CPU
8-bit register-register multiply:
the product.
8-bit register-register divide:
16-bit register-register multiply:
16-bit register-register divide:
20 MHz*
150 ns (H8S/2000 CPU: 600 ns)
600 ns
200 ns (H8S/2000 CPU: 1000 ns)
1000 ns
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