M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 22

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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2.2 High-Speed Interrupt Registers
2.3 DMAC-Associated Registers
3
. v
J
2
0
1
C
3
4 .
B
8 /
Registers associated with the high-speed interrupt are as follows. Refer to 10.4 High-Speed Interrupt for
details.
Registers associated with DMAC are as follows. Refer to 12. DMAC for details.
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
0
1
2.1.8.5 Register Bank Select Flag (B)
2.1.8.6 Overflow Flag (O)
2.1.8.7 Interrupt Enable Flag (I)
2.1.8.8 Stack Pointer Select Flag (U)
2.1.8.9 Processor Interrupt Priority Level (IPL)
2.1.8.10 Reserved Space
3
0
1
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag
is set to "0" when an interrupt is acknowledged.
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
When writing to a reserved space, set to "0". When read, its content is indeterminate.
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