AT90USB162-16MUR Atmel, AT90USB162-16MUR Datasheet - Page 193
AT90USB162-16MUR
Manufacturer Part Number
AT90USB162-16MUR
Description
IC AVR MCU 16K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB82-16MU.pdf
(307 pages)
Specifications of AT90USB162-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFN
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
AT90USB162-16MURTR
AT90USB162-16MUTR
AT90USB162-16MUTR
AT90USB162-16MUTR
AT90USB162-16MUTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB162-16MUR
Manufacturer:
TT
Quantity:
400 000
- Current page: 193 of 307
- Download datasheet (4Mb)
19.9
19.9.1
7707F–AVR–11/10
Registers description
USB general registers
• 7 – USBE: USB macro Enable Bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – Reserved
The value read from this bit is always 0. Do not set this bit.
• 5 – FRZCLK: Freeze USB Clock Bit
Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power
consumption. Clear to enable the clock inputs.
• 4-0 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 7 – DPACC: DPRAM Direct Access Bit
Set this bit to directly read the content the Dual-Port RAM (DPR) data through the UEDATX or
UPDATX registers. See Section 19.6, page 190 for more details.
Clear this bit for normal operation and access the DPR through the endpoint FIFO.
• 6-0 – Reserved
The value read from these bits is always 0. Do not set these bits.
Bit
Read/Writ
e
Initial Val-
ue
Bit
Read/Wr
ite
Initial
Value
Bit
Read/Writ
e
Initial Val-
ue
7
DPACC
R/W
0
7
USBE
R/W
0
7
DPADD7:0
R/W
0
6
-
R
0
6
-
R
0
6
R/W
0
5
-
R
0
5
FRZLK
R/W
1
5
R/W
0
4
-
R
0
4
-
R
0
4
R/W
0
3
-
R
0
3
-
R
0
3
R/W
0
2
-
R
0
2
-
R
0
2
R/W
0
1
-
R
0
1
-
R
0
AT90USB82/162
1
R/W
0
0
-
R
0
0
-
R
0
0
R/W
0
USBCON
UDPADDH
UDPADDL
193
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