MC908SR12MFAER Freescale Semiconductor, MC908SR12MFAER Datasheet - Page 128
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MC908SR12MFAER
Manufacturer Part Number
MC908SR12MFAER
Description
IC MCU 12K FLASH 4/8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12MFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
MC908SR12MFAER
MC908SR12MFAERTR
MC908SR12MFAERTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908SR12MFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 128 of 404
- Download datasheet (2Mb)
Clock Generator Module (CGM)
8.6.1 PLL Control Register
Data Sheet
128
NOTE:
Address:
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
$0036
PLLIE
Bit 7
0
Clock Generator Module (CGM)
Figure 8-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
PLLON
5
1
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
BCS
4
0
PRE1
3
0
PRE0
Freescale Semiconductor
2
0
VPR1
1
0
VPR0
Bit 0
0
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