MC908SR12MFAER Freescale Semiconductor, MC908SR12MFAER Datasheet - Page 247
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC908SR12MFAER
Manufacturer Part Number
MC908SR12MFAER
Description
IC MCU 12K FLASH 4/8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908SR12MFAE.pdf
(404 pages)
Specifications of MC908SR12MFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, Temp Sensor
Number Of I /o
31
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
MC908SR12MFAER
MC908SR12MFAERTR
MC908SR12MFAERTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908SR12MFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Addr.
Addr.
$005A
$005A
$0059
$0059
ADC Data Register High 0
ADC Data Register High 0
ADC Data Register Low 0
ADC Data Register Low 0
Register Name
Register Name
Figure 15-8. ADRH0 and ADRL0 in Left Justified Sign Data Mode
(ADRH0)
(ADRH0)
(ADRL0)
(ADRL0)
Figure 15-7. ADRH0 and ADRL0 in Left Justified Mode
In left justified mode the ADRH0 holds the eight most significant bits
(MSBs), and the ADRL0 holds the two least significant bits (LSBs), of the
10-bit result. The ADRH0 and ADRL0 are updated each time a single
channel ADC conversion completes. Reading ADRH0 latches the
contents of ADRL0. Until ADRL0 is read all subsequent ADC results will
be lost. (See
In left justified sign mode the ADRH0 holds the eight MSBs with the MSB
complemented, and the ADRL0 holds the two least significant bits
(LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each
time a single channel ADC conversion completes. Reading ADRH0
latches the contents of ADRL0. Until ADRL0 is read all subsequent ADC
results will be lost. (See
Justified Sign Data
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 7
AD9
AD1
AD9
AD1
Analog-to-Digital Converter (ADC)
R
R
R
R
0
0
0
0
Figure 15-7 . ADRH0 and ADRL0 in Left Justified
AD8
AD0
AD8
AD0
R
R
R
R
6
0
0
6
0
0
Mode.)
Figure 15-8 . ADRH0 and ADRL0 in Left
AD7
AD7
R
R
R
R
5
0
0
0
5
0
0
0
AD6
AD6
R
R
R
R
4
0
0
0
4
0
0
0
AD5
AD5
R
R
R
R
3
0
0
0
3
0
0
0
Analog-to-Digital Converter (ADC)
AD4
AD4
R
R
R
R
2
0
0
0
2
0
0
0
AD3
AD3
R
R
R
R
1
0
0
0
1
0
0
0
I/O Registers
Data Sheet
Mode.)
Bit 0
Bit 0
AD2
AD2
R
R
R
R
0
0
0
0
0
0
247
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