PIC12F519-I/P Microchip Technology, PIC12F519-I/P Datasheet - Page 40
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PIC12F519-I/P
Manufacturer Part Number
PIC12F519-I/P
Description
IC PIC MCU FLASH 1KX12 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F519-ISN.pdf
(96 pages)
2.PIC12F519-ISN.pdf
(4 pages)
3.PIC12F519-ISN.pdf
(22 pages)
4.PIC12F519-IP.pdf
(88 pages)
Specifications of PIC12F519-I/P
Program Memory Type
FLASH
Program Memory Size
1.5KB (1K x 12)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Peripherals
POR, WDT
Number Of I /o
5
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Interface Type
USB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
Package
8PDIP
Device Core
PIC
Family Name
PIC12
Maximum Speed
8 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162096 - HEADER MPLAB ICD2 PIC16F526 8/14AC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F519-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC12F519
REGISTER 8-1:
DS41319B-page 38
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1: Refer to the “PIC12F519 Memory Programming Specification”, DS41316 to determine how to
—
2: DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application
program/erase the Configuration Word.
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in
acceptable operation. Refer to Figure 11-1 and Table 11-2 for V
this mode of operation.
Unimplemented: Read as ‘1’
CPDF: Code Protection bit - Flash Data Memory
1 = Code protection off
0 = Code protection on
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC frequency
0 = 4 MHz INTOSC frequency
MCLRE: Master Clear Enable bit
1 = GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to V
CP: Code Protection bit - User Program Memory
1 = Code protection off
0 = Code protection on
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<1:0>: Oscillator Selection bits
00 = LP oscillator with 18 ms DRT
01 = XT oscillator with 18 ms DRT
10 = INTOSC with 1 ms DRT
11 = EXTRC with 1 ms DRT
CPDF
CONFIG: CONFIGURATION WORD REGISTER
IOSCFS
(2)
(2)
MCLRE
(2)
(2)
CP
DD
(1)
WDTE
rise time and stability requirements for
DD
© 2008 Microchip Technology Inc.
FOSC1
FOSC0
bit 0