PIC12F615-I/MD Microchip Technology, PIC12F615-I/MD Datasheet - Page 33

• Manufacturer Part Number: PIC12F615-I/MD
• Description: IC PIC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F615-I/MD

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Digital Ic Case Style: DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.0
There are as many as six general purpose I/O pins
available. Depending on which peripherals are enabled,
some or all of the pins may not be available as general
purpose I/O. In general, when a peripheral is enabled,
the associated pin may not be used as a general
purpose I/O pin.
4.1
GPIO is a 6-bit wide port with 5 bidirectional and 1
input-only pin. The corresponding data direction register
is TRISIO (Register 4-2). Setting a TRISIO bit (= 1) will
make the corresponding GPIO pin an input (i.e., disable
the output driver). Clearing a TRISIO bit (= 0) will make
the corresponding GPIO pin an output (i.e., enables
output driver and puts the contents of the output latch on
the selected pin). The exception is GP3, which is input
only and its TRIS bit will always read as ‘1’. Example 4-1
shows how to initialize GPIO.
Reading the GPIO register (Register 4-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
REGISTER 4-1:
REGISTER 4-2:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1:
U-0
U-0
—
—
2:
I/O PORT
GPIO and the TRISIO Registers
TRISIO<3> always reads ‘1’.
TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Unimplemented: Read as ‘0’
GP<5:0>: GPIO I/O Pin bit
1 = GPIO pin is > V
0 = GPIO pin is < V
Unimplemented: Read as ‘0’
TRISIO<5:0>: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
U-0
U-0
—
—
GPIO: GPIO REGISTER
TRISIO: GPIO TRI-STATE REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRISIO5
IH
IL
R/W-1
R/W-x
GP5
PIC12F609/615/12HV609/615
TRISIO4
R/W-0
R/W-1
GP4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRISIO3
port pins are read, this value is modified and then
written to the PORT data latch. GP3 reads ‘0’ when
MCLRE = 1.
The TRISIO register controls the direction of the
GPIO pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
EXAMPLE 4-1:
GP3
R-x
R-1
BANKSEL
CLRF
BANKSEL
CLRF
MOVLW
MOVWF
Note:
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
GPIO
GPIO
ANSEL
ANSEL
0Ch
TRISIO
TRISIO2
R/W-0
R/W-1
GP2
INITIALIZING GPIO
;
;Init GPIO
;
;digital I/O, ADC clock
;setting ‘don’t care’
;Set GP<3:2> as inputs
x = Bit is unknown
x = Bit is unknown
;and set GP<5:4,1:0>
;as outputs
TRISIO1
R/W-0
R/W-1
GP1
DS41302A-page 31
TRISIO0
R/W-0
R/W-1
GP0
bit 0
bit 0