PIC16F1827-I/P Microchip Technology, PIC16F1827-I/P Datasheet - Page 6

• Manufacturer Part Number: PIC16F1827-I/P
• Description: IC PIC MCU FLASH 4K 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1827-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16(L)F1826/1827
EXAMPLE 1:
For other combinations of F
Instruction cycle delay counts, refer to
TABLE 3:
DS80485G-page 6
BSF
BCF
MOVF
Note:
F
F
F
Affected Silicon Revisions
OSC
OSC
OSC
A2
T
X
AD
ADCON0, ADGO
ADCON0, ADGO
ADRESH, W
/64
/32
/16
The exact delay time will depend on the
T
counts shown in the timing diagram above
apply to this example only. Refer to
Table 3
other configurations.
A3
AD
X
INSTRUCTION CYCLE DELAY
COUNTS BY T
divisor (ADCS) selection. The T
Instruction Cycle Delay Counts
A4
CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
for the required delay counts for
; Start ADC conversion
; Provide 86
; Terminate the
; Read conversion
instruction cycle
delay here
conversion manually
result
OSC
AD
172
86
43
, T
SELECTION
AD
Table
values and
3.
CY
6. Module: Enhanced Capture Compare
6.1 Enhanced PWM
6.2 Enhanced PWM
When the PWM is configured for Full-Bridge mode
and the duty cycle is set to 0%, writing the
PxM<1:0> bits to change the direction has no
effect on PxA and PxC outputs.
Work around
Increase the duty cycle to a value greater than 0%
before changing directions.
Affected Silicon Revisions
In PWM mode, when the duty cycle is set to 0%
and the STRxSYNC bit is set, writing the STRxA,
STRxB, STRxC and the STRxD bits to enable/
disable steering to port pins has no effect on the
outputs.
Work around
Increase the duty cycle to a value greater than 0%
before enabling/disabling steering to port pins.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
PWM (ECCP)
A4
A4
 2011 Microchip Technology Inc.