PIC16LC620A-04/P Microchip Technology, PIC16LC620A-04/P Datasheet - Page 22
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PIC16LC620A-04/P
Manufacturer Part Number
PIC16LC620A-04/P
Description
IC MCU OTP 512X14 COMP 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16C620A-04SO.pdf
(128 pages)
Specifications of PIC16LC620A-04/P
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
13
Program Memory Size
896B (512 x 14)
Program Memory Type
OTP
Ram Size
96 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-DIP (0.300", 7.62mm)
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
96 B
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
PIC16LC620A-04/PR
PIC16LC620A-04/PR
PIC16LC620A-04/PR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC620A-04/P
Manufacturer:
SAM
Quantity:
4 694
PIC16C62X
4.2.2.3
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See
description of the comparator enable and flag bits.
REGISTER 4-3:
DS30235J-page 20
Section 4.2.2.4
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON Register
INTCON REGISTER (ADDRESS 0BH OR 8BH)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
Legend:
R = Readable bit
- n = Value at POR
and
R/W-0
GIE
Section 4.2.2.5
R/W-0
PEIE
for
R/W-0
T0IE
W = Writable bit
’1’ = Bit is set
a
R/W-0
INTE
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
RBIE
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
R/W-0
T0IF
2003 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
R/W-x
RBIF
bit 0