PIC18F14K50-I/P Microchip Technology, PIC18F14K50-I/P Datasheet - Page 169
PIC18F14K50-I/P
Manufacturer Part Number
PIC18F14K50-I/P
Description
IC PIC MCU FLASH 8KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(10 pages)
3.PIC18F13K50-ISS.pdf
(2 pages)
4.PIC18F14K50-ISS.pdf
(4 pages)
5.PIC18F14K50-IP.pdf
(422 pages)
Specifications of PIC18F14K50-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/MSSP/SPI/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
20PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F14K50-ISS PDF datasheet #4
- PIC18F14K50-IP PDF datasheet #5
- Current page: 169 of 420
- Download datasheet (4Mb)
15.3.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (T
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator
times out (T
will be automatically cleared by hardware; the Baud
Rate Generator is suspended, leaving the SDA line
held low and the Start condition is complete.
FIGURE 15-19:
2010 Microchip Technology Inc.
BRG
I
CONDITION TIMING
BRG
2
is
C MASTER MODE START
), the SEN bit of the SSPCON2 register
), the SDA pin is driven low. The action
reloaded
Write to SEN bit occurs here
FIRST START BIT TIMING
with
SDA
SCL
the
contents
SDA = 1,
SCL = 1
T
BRG
Preliminary
of
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
15.3.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
Note:
T
Write to SSPBUF occurs here
BRG
PIC18F/LF1XK50
1st bit
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I
state.
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
T
BRG
2
C module is reset into its Idle
2nd bit
DS41350E-page 169
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