PIC18F2220-I/SP Microchip Technology, PIC18F2220-I/SP Datasheet - Page 38
![IC MCU FLASH 2KX16 A/D 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2220-I/SP
Manufacturer Part Number
PIC18F2220-I/SP
Description
IC MCU FLASH 2KX16 A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2220-ISO.pdf
(394 pages)
3.PIC18F2220-ISO.pdf
(6 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(8 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISP.pdf
(388 pages)
Specifications of PIC18F2220-I/SP
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI/I2C/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
5
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2220-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2220-ISO PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISP PDF datasheet #8
- Current page: 38 of 394
- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
3.4
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Wake-up from a power-managed Run mode can be
triggered by an interrupt, or any Reset, to return to full-
power operation. As the CPU is executing code in Run
modes, several additional exits from Run modes are
possible. They include exit to Sleep mode, exit to a cor-
responding Idle mode, and exit by executing a RESET
instruction. While the device is in any of the power-
managed Run modes, a WDT time-out will result in a
WDT Reset.
3.4.1
The PRI_RUN mode is the normal full-power execution
mode. If the SLEEP instruction is never executed, the
microcontroller operates in this mode (a SLEEP instruc-
tion is executed to enter all other power-managed
modes). All other power-managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
FIGURE 3-9:
DS39599G-page 36
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Run Modes
Q1
PRI_RUN MODE
SEC_RUN MODE
Q2
PC
Q3
Q4
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q1
1
2
3
Clock Transition
4
5
PC + 2
6
7
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
When a wake-up event occurs, the peripherals and
CPU continue to be clocked from the Timer1 oscillator
while the primary clock is started. When the primary
clock becomes ready, a clock switch back to the primary
clock occurs (see Figure 3-6). When the clock switch is
complete, the T1RUN bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full-power operation is trig-
gered. The Timer1 oscillator will continue to run and
provide the system clock even though the T1OSCEN bit
is cleared. The primary clock is started. When the
primary clock becomes ready, a clock switch back to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
Note:
8
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when try-
ing to set the SCS0 bit, the write to
SCS0 will not occur. If the Timer1 oscilla-
tor is enabled, but not yet running, system
clocks will be delayed until the oscillator
has started; in such situations, initial oscil-
lator operation is far from stable and
unpredictable operation may result.
Q2
Q3
© 2007 Microchip Technology Inc.
Q4
Q1
PC + 2
Q2
Q3
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