DSPIC30F4013-30I/ML Microchip Technology, DSPIC30F4013-30I/ML Datasheet - Page 151

• Manufacturer Part Number: DSPIC30F4013-30I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44QFN EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401330IML

20.4
The
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 20-2:
20.4.1
A power-on event generates an internal POR pulse
when a V
the POR circuit threshold voltage (V
inally 1.85V. The device supply voltage characteristics
must meet specified starting voltage and rise rate
requirements. The POR pulse resets a POR timer and
places the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
 2010 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
MCLR
V
dsPIC30F3014/4013
DD
Reset
DD
Instruction
RESET
POR: POWER-ON RESET
rise is detected. The Reset pulse occurs at
Trap Conflict
Illegal Opcode/
Uninitialized W Register
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
differentiates
BOREN
Glitch Filter
Digital
POR
POR
) which is nom-
BOR
between
Different registers are affected in different ways by var-
ious Reset conditions. Most registers are not affected
by a WDT wake-up since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in
used in software to determine the nature of the Reset.
A block diagram of the On-Chip Reset Circuit is shown
in
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
The POR circuit inserts a small delay, T
nominally 10 s and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms, or 64 ms. The
total delay is at device power-up, T
these delays have expired, SYSRST is negated on the
next leading edge of the Q1 clock and the PC jumps to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3
Figure
dsPIC30F3014/4013
20-2.
through
Figure
S
R
PWRT
Table
20-5.
) is applied. The T
Q
20-5. These bits are
POR
DS70138G-page 151
+ T
SYSRST
POR
PWRT
, which is
. When
PWRT