PIC18F4439-I/P Microchip Technology, PIC18F4439-I/P Datasheet - Page 76
![IC MCU FLASH 6KX16 EE A/D 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4439-I/P
Manufacturer Part Number
PIC18F4439-I/P
Description
IC MCU FLASH 6KX16 EE A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F4439-I/P
Core Size
8-Bit
Program Memory Size
12KB (6K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
640 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
32
Eeprom Memory Size
256Byte
Ram Memory Size
640Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
640 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4439-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 76 of 322
- Download datasheet (7Mb)
PIC18FXX39
8.2
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag registers (PIR1, PIR2).
REGISTER 8-4:
DS30485A-page 74
PIR Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
PSPIF
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit (see Section 17.0 for details on TXIF functionality)
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
Unimplemented: Read as ‘0’
TMR2IF
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = MR1 register did not overflow
Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear.
bit 7
Legend:
R = Readable bit
- n = Value at POR
PSPIF
R/W-0
2: This bit is reserved for use by the ProMPT kernel; do not alter its value.
(1)
(1)
(2)
: Parallel Slave Port Read/Write Interrupt Flag bit
: TMR2 to PR2 Match Interrupt Flag bit
R/W-0
ADIF
RCIF
R-0
Preliminary
W = Writable bit
‘1’ = Bit is set
TXIF
R-0
Note 1: Interrupt flag bits are set when an interrupt
2: User software should ensure the appropri-
SSPIF
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
U-0
—
2002 Microchip Technology Inc.
TMR2IF
R/W-0
x = Bit is unknown
(2)
TMR1IF
R/W-0
bit 0
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