EP9315-IB Cirrus Logic Inc, EP9315-IB Datasheet - Page 174
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122388/ep9315-ib_sml.jpg)
EP9315-IB
Manufacturer Part Number
EP9315-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1262
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
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6
VICxIntEnClear
VICxSoftInt
6-12
Vectored Interrupt Controller
EP93xx User’s Guide
31
15
31
15
Definition:
Bit Descriptions:
Address:
Default: Don’t Care
Definition:
Bit Descriptions:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
Interrupt Enable Register. The VICxIntEnable register enables the interrupt
requests by unmasking the interrupt sources. On reset, all interrupts are
disabled (masked).
IntEnable:
VIC1IntEnClear: 0x800B_0014 - Write Only
VIC2IntEnClear: 0x800C_0014 - Write Only
Interrupt Enable Clear Register. The VICxIntEnClear register clears bits in the
VICxIntEnable register.
VIC1SoftInt: 0x800B_0018 - Read/Write
VIC2SoftInt: 0x800C_0018 - Read/Write
IntEnable Clear:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Enables the interrupt request lines:
1 - Interrupt enabled. Allows interrupt request to ARM
Core.
0 - Interrupt disabled.
Clears bits in the VICxIntEnable register. Writing a bit to
“1” clears the corresponding bit in the VICxIntEnable
register. Any bits written to “0” have no effect.
IntEnable Clear
IntEnable Clear
24
24
8
8
SoftInt
SoftInt
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0
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