EP9315-IB Cirrus Logic Inc, EP9315-IB Datasheet - Page 423
EP9315-IB
Manufacturer Part Number
EP9315-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1262
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
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MAXCNTx
BASEx
DS785UM1
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
30
14
30
14
29
13
29
13
28
12
28
12
MAXCNT0: Channel Base Address + 0x0020 - Read/Write
MAXCNT1: Channel Base Address + 0x0030 - Read/Write
x = “0” or “1”. Maximum byte count for the buffer. Represents the double buffer
per channel. Only the low order 16 bits are used. Each MAXCNTx register
must be programmed before it’s corresponding BASEx register.
RSVD:
MAXCNTx:
BASE0: Channel Base Address + 0x0024 - Read/Write
BASE1: Channel Base Address + 0x0034 - Read/Write
Base address for the current and next DMA transfer.
BASEx:
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved. Unknown During Read.
Maximum byte count for the buffer.
x = “0” or “1”. Base address for the current and next DMA
transfer. Loaded with start address after enabling the DMA
Channel, the latter event required to take the Channel
State machine into the STALL state, the former event
required to enter the ON State.
24
24
8
MAXCNTx
8
BASEx
BASEx
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
18
18
2
2
DMA Controller
17
17
1
1
10-29
16
16
0
0
10
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