Z8F0413SH005EC Zilog, Z8F0413SH005EC Datasheet - Page 37

• Manufacturer Part Number: Z8F0413SH005EC
• Description: IC ENCORE MCU FLASH 4K 20SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413SH005EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3486

Table 11. Stop Mode Recovery Sources and Resulting Action
PS024314-0308
Operating Mode Stop Mode Recovery Source
STOP mode
Note:
Caution:
Stop Mode Recovery Using Watchdog Timer Time-Out
Stop Mode Recovery Using a GPIO Port Pin Transition
vector address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer
Control Register is set to 1.
actions. The section following the table provides more detailed information on each of the
Stop Mode Recovery sources.
If the Watchdog Timer times out during STOP mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
Z8 Encore! XP
services the Watchdog Timer interrupt request following the normal Stop Mode Recovery
sequence.
Each of the GPIO port pins can be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
The SMR pulses shorter than specified does not trigger a recovery. When this happens, the
STOP bit in the Reset Status (RSTSTAT) register is set to 1.
Watchdog Timer time-out when configured
for Reset
Watchdog Timer time-out when configured
for interrupt
Data transition on any GPIO port pin
enabled as a Stop Mode Recovery source
Assertion of external
Debug Pin driven Low
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the port transition only if the signal stays on the port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can
initiate Stop Mode Recovery without being written to the Port Input Data register or
without initiating an interrupt (if enabled for that pin).
®
F0823 Series device is configured to respond to interrupts, the eZ8 CPU
RESET
Table 11
Pin
lists the Stop Mode Recovery sources and resulting
Action
Stop Mode Recovery
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Stop Mode Recovery
System Reset
System Reset
Z8 Encore! XP
Reset and Stop Mode Recovery
Product Specification
®
F0823 Series
27