C8051T603-GM Silicon Laboratories Inc, C8051T603-GM Datasheet - Page 118
![IC 8051 MCU 4K-EEPROM 11-QFN](/photos/12/25/122557/c8051t603-gm_sml.jpg)
C8051T603-GM
Manufacturer Part Number
C8051T603-GM
Description
IC 8051 MCU 4K-EEPROM 11-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T603-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
8
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1656-5
- Current page: 118 of 188
- Download datasheet (898Kb)
C8051T600/1/2/3/4/5/6
22.5. Special Function Registers for Accessing and Configuring Port I/O
The Port I/O pins are accessed through the special function register P0, which is both byte addressable
and bit addressable. When writing to this SFR, the value written is latched to maintain the output data
value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the
XBRn settings (i.e., even when the pin is assigned to another signal by the crossbar, the Port register can
always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write
instructions that target the Port 0 Latch register as the destination. The read-modify-write instructions
include ANL, ORL, XRL, JBC, CPL, INC, DEC, or DJNZ for any usage. However, when the destination is
an individual bit in P0, the read-modify-write instructions include MOV, CLR, or SETB. For all read-modify-
write instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR.
The XBR0 register allows the individual Port pins to be assigned to digital functions or skipped by the
crossbar. All Port pins used for analog functions, GPIO, or dedicated digital functions should have their
XBR0 bit set to 1.
The Port input mode of the I/O pins is defined using the Port 0 Input Mode register (P0MDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers and is not automatic.
The output driver characteristics of the I/O pins are defined using the Port 0 Output Mode register
(P0MDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
P0MDOUT settings.
SFR Definition 22.4. P0: Port 0
SFR Address = 0x80; Bit-Addressable
118
Name
Reset
7:0
Bit
Type
Bit
P0[7:0]
Name
7
1
Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Note: Bits 6 and 0 on the C8051T606 are read-only.
6
1
Description
5
1
Rev. 1.2
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
1
P0[7:0]
R/W
Write
3
1
2
1
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
1
1
Read
0
1
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