C8051T603-GM Silicon Laboratories Inc, C8051T603-GM Datasheet - Page 169
![IC 8051 MCU 4K-EEPROM 11-QFN](/photos/12/25/122557/c8051t603-gm_sml.jpg)
C8051T603-GM
Manufacturer Part Number
C8051T603-GM
Description
IC 8051 MCU 4K-EEPROM 11-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T603-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
8
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1656-5
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26.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit Capture/Compare
module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter
matches the module contents, the output on CEXn is asserted high; when the 16-bit counter overflows,
CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA
CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in
the PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND
MATn = 1) to help synchronize the Capture/Compare register writes. If the MATn bit is set to 1, the CCFn
flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. The CF flag in
PCA0CN can be used to detect the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given
by Equation 26.3.
Important Note about Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Using Equation 26.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
P
W
M
1
6
n
1
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
A
P
N
n
M
A
T
n
PCA Timebase
O
G
T
n
Equation 26.3. 16-Bit PWM Duty Cycle
P
W
M
n
E
C
C
F
n
x
Figure 26.9. PCA 16-Bit PWM Mode
Duty Cycle
Enable
PCA0CPHn
PCA0H
=
16-bit Comparator
Rev. 1.2
---------------------------------------------------- -
65536 PCA0CPn
PCA0CPLn
PCA0L
–
65536
C8051T600/1/2/3/4/5/6
Overflow
match
S
R
SET
CLR
Q
Q
CEXn
Crossbar
Port I/O
169
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