C8051T631-GM Silicon Laboratories Inc, C8051T631-GM Datasheet - Page 33
![IC MCU 8KB 20PIN QFN](/photos/12/25/122567/silicon_laboratories_inc-20-qfn_sml.jpg)
C8051T631-GM
Manufacturer Part Number
C8051T631-GM
Description
IC MCU 8KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T631-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
UART, SPI, SMBus
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4 x 16-bit
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1459-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T631-GM
Manufacturer:
Silicon
Quantity:
91
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6. 10-Bit ADC (ADC0, C8051T630/2/4 only)
ADC0 on the C8051T630/2/4 is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector.
The ADC is fully configurable under software control via Special Function Registers. The ADC may be con-
figured to measure various different signals using the analog multiplexer described in Section “6.5. ADC0
Analog Multiplexer (C8051T630/2/4 only)” on page 43. The voltage reference for the ADC is selected as
described in Section “9. Voltage Reference Options” on page 52. The ADC0 subsystem is enabled only
when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in
low power shutdown when this bit is logic 0.
AMUX0
From
X1 or
X0.5
AMP0GN0
Figure 6.1. ADC0 Functional Block Diagram
AIN
ADC0CF
ADC
10-Bit
VDD
SAR
Rev. 1.0
ADC0GTH ADC0GTL
ADC0LTH
ADC0CN
C8051T630/1/2/3/4/5
ADC0LTL
Conversion
Start
000
001
010
011
100
101
32
AD0WINT
Compare
Window
CNVSTR Input
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Timer 3 Overflow
Logic
33
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