C8051T631-GM Silicon Laboratories Inc, C8051T631-GM Datasheet - Page 48

• Manufacturer Part Number: C8051T631-GM
• Description: IC MCU 8KB 20PIN QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T63xr

Specifications of C8051T631-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: UART, SPI, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T630DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1464 - KIT DEV FOR C8051T630 FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1459-5

C8051T630/1/2/3/4/5
8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only)
The C8051T630/2/4 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maxi-
mum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and
2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Defini-
tion 8.1). When IDA0EN is set to 0, the IDAC port pin (P0.1) behaves as a normal GPIO pin. When
IDA0EN is set to 1, the digital output drivers and weak pullup for the IDAC pin are automatically disabled,
and the pin is connected to the IDAC output. An internal bandgap bias generator is used to generate a ref-
erence current for the IDAC whenever it is enabled. When using the IDAC, bit 1 in the P0SKIP register
should be set to 1, to force the Crossbar to skip the IDAC pin.
8.1. IDA0 Output Scheduling
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and sup-
ports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output
updates on a write to IDA0H, on a Timer overflow, or on an external pin edge.
8.1.1. Update Output On-Demand
In its default mode (IDA0CN.[6:4] = 111) the IDA0 output is updated “on-demand” on a write to the high-
byte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode,
and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the
IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data reg-
isters. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be
IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by
initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see Section 8.2 for
information on the format of the 10-bit IDAC data word within the 16-bit SFR space).
48
IDA0OMD1
IDA0OMD0
IDA0CM2
IDA0CM1
IDA0CM0
IDA0EN
Figure 8.1. IDA0 Functional Block Diagram
8
2
10
Rev. 1.0
IDA0
IDA0