C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 276

IC 8051 MCU 32K FLASH 28-QFN

C8051F365-GM

Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Datasheets

Specifications of C8051F365-GM

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F360/1/2/3/4/5/6/7/8/9
22.4. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
276
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SFR Page:
SFR Address:
R/W
CF
Bit7
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vec-
tor to the CF interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
CCF5: PCA0 Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
all pages
0xD8
R/W
CR
Bit6
SFR Definition 22.1. PCA0CN: PCA Control
CCF5
R/W
Bit5
(bit addressable)
CCF4
R/W
Bit4
Rev. 1.0
CCF3
R/W
Bit3
CCF2
R/W
Bit2
CCF1
R/W
Bit1
CCF0
R/W
Bit0
00000000
Reset Value

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