DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet
DF2214BQ16V
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DF2214BQ16V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2214 Group 16 Hardware Manual Renesas 16-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of this Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of this Manual 3. Overview 4. Table of Contents 5. Summary 6. Description of Functional Modules • CPU and ...
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This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data ...
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H8S/2214 Group Manuals: Document Title H8S/2214 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual User’s Manuals for Development Tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User’s Manual H8S, H8/300 Series Simulator/Debugger (for Windows) User’s ...
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Main Revisions for This Edition Item Page 1.3.2 Pin Functions Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode 2.3 Address Space 25 Figure 2.6 Memory Map Revisions (See Manual for Details) Note added ...
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Item Page 2.6.1 Overview 34 Table 2.1 Instruction Classification 2.6.2 Instructions 35 and Addressing Modes Table 2.2 Combinations of Instructions and Addressing Modes 2.6.3 Table of 38 Instructions Classified by Function Table 2.3 Instructions Classified by 40 Function 46 Rev.4.00 ...
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Item Page 2.6.5 Notes on Use 48 of Bit-Manipulation Instructions 2.8.1 Overview 56 Figure 2.15 Processing States Figure 2.16 State 57 Transitions 5.1.2 Block 92 Diagram Figure 5.1 Block Diagram of Interrupt Controller Revisions (See Manual for Details) Description added ...
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Item Page 5.3.1 External 100 Interrupts Figure 5.3 Timing of Setting IRQnF 5.5.1 Contention 113 between Interrupt Generation and Disabling 5.5.5 IRQ 115 Interrupts 5.5.6 NMI Interrupt 115 Usage Notes 6.1.2 Block 120 Diagram Figure 6.1 Block Diagram of Bus ...
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Item Page 7.5.9 DMAC Bus 234 Cycles (Dual Address Mode) (2) Full Address Mode (Cycle Steal Mode) 8.2.5 DTC Transfer 258 Count Register A (CRA) 8.3.1 Overview 262 Figure 8.2 Flowchart of DTC Operation 8.3.2 Activation 264 Sources Revisions (See ...
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Item Page 8.3.8 Chain 273 Transfer 8.5 Usage Notes 280 (1) Module Stop 9.2.2 Register 286 Configuration (1) Port 1 Data Direction Register (P1DDR) 9.3.2 Register 297 Configuration (1) Port 3 Data Direction Register (P3DDR) 9.5.2 Register 309 Configuration (1) ...
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Item Page 9.8.2 Register 323 Configuration (1) Port B Data Direction Register (PBDDR) 9.9.2 Register 331 Configuration (1) Port C Data Direction Register (PCDDR) 9.10.2 Register 338 Configuration (1) Port D Data Direction Register (PDDDR) 9.11.2 Register 343 Configuration (1) ...
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Item Page 9.14 Handling of 358 Unused Pins 10.2.1 Timer 368 Control Register (TCR) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0) 10.2.5 Timer 383 Status Register (TSR) Bit 3—Input Capture/Output Compare Flag D (TGFD) Bit 2—Input Capture/Output ...
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Item Page 10.7 Usage Notes 427 (1) Module Stop Mode Settings Figure 10.53 436 Contention between TCNT Write and Overflow 11.5.5 OVF Flag 451 Clear Operation in Interval Timer Mode 12.2.7 Serial 468 Status Register (SSR) Bit 7—Transmit Data Register ...
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Item Page 12.2.7 Serial 470 Status Register (SSR) Bit 2—Transmit End (TEND) 12.3.2 Operation in 493 Asynchronous Mode Figure 12.7 Sample SCI Initialization Flowchart Rev.4.00 Sep. 18, 2008 Page xvi of lx REJ09B0189-0400 Revisions (See Manual for Details) Note added ...
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Item Page 12.3.2 Operation in 494 Asynchronous Mode Figure 12.8 Sample Serial Transmission Flowchart Revisions (See Manual for Details) Note added Initialization Start transmission Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and ...
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Item Page 12.3.2 Operation in 497 Asynchronous Mode Figure 12.10 Sample Serial Reception Data Flowchart (1) Rev.4.00 Sep. 18, 2008 Page xviii of lx REJ09B0189-0400 Revisions (See Manual for Details) Note added Initialization Start reception Read ORER, PER, and FER ...
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Item Page 12.3.3 503 Multiprocessor Communication Function Figure 12.14 Sample Multiprocessor Serial Transmission Flowchart Revisions (See Manual for Details) Note added Initialization Start transmission Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and ...
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Item Page 12.3.4 Operation in 512 Clocked Synchronous Mode Figure 12.21 Sample Serial Transmission Flowchart Rev.4.00 Sep. 18, 2008 Page REJ09B0189-0400 Revisions (See Manual for Details) Note added Initialization Start transmission Read TDRE flag in SSR No ...
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Item Page 12.3.4 Operation in 515 Clocked Synchronous Mode Figure 12.23 Sample Serial Reception Flowchart Revisions (See Manual for Details) Note added Initialization Start reception Read ORER flag in SSR ORER = 1 No Error processing (Continued below) Read RDRF ...
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Item Page 12.3.4 Operation in 517 Clocked Synchronous Mode Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.4.00 Sep. 18, 2008 Page xxii of lx REJ09B0189-0400 Revisions (See Manual for Details) Note added Initialization Start transmission/reception Read ...
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Item Page 12.4 SCI Interrupts 518 12.5 Usage Notes 520 (1) Module Stop Mode Settings (8) Restrictions on 523 Use of DMAC or DTC 17.6.3 Setting 630 Oscillation Stabilization Time after Clearing Software Standby Mode Table 17.4 Oscillation Stabilization Time ...
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Item Page A.1 Instruction List 665 Table A.1 Data Transfer Instructions Table A.2 669 Arithmetic Instructions A.4 Number of 711 States Required for Instruction Execution Table A.15 Number of Cycles in Instruction Execution 715 716 Rev.4.00 Sep. 18, 2008 Page ...
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Item Page A.5 Bus States 724 during Instruction Execution Table A.16 Instruction Execution Cycles 729 730 A.6 Condition 733 Code Modification Table A.17 Condition Code 735 Modification 736 B.2 Functions 785 TCR1—Timer Control Register 1 Revisions (See Manual for Details) ...
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Item Page B.2 Functions 791 TCR2—Timer Control Register 2 TCSR0—Timer 801 Control/Status Register Rev.4.00 Sep. 18, 2008 Page xxvi of lx REJ09B0189-0400 Revisions (See Manual for Details) Description added Clock Edge 1 and Count at rising edge ...
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Item Page B.2 Functions 807 SSR0—Serial Status Register 0 Revisions (See Manual for Details) Note added Bit : TDRE RDRF ORER FER Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* ...
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Item Page B.2 Functions 813 SSR1—Serial Status Register 1 Rev.4.00 Sep. 18, 2008 Page xxviii of lx REJ09B0189-0400 Revisions (See Manual for Details) Note added Bit : TDRE RDRF ORER Initial value : ...
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Item Page B.2 Functions 819 SSR2—Serial Status Register 2 Revisions (See Manual for Details) Note added Bit : TDRE RDRF ORER Initial value : R/W : R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer ...
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Item Page 835 C.3 Port 4 Block Diagram Figure C.9 Port 4 Block Diagram (Pins P40 to P44, P46, and P47) Figure C.10 Port 4 Block Diagram (Pin P45) Appendix G 869 Package Dimensions Figure G.1 TFP- 100B, TFP-100BV Package ...
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Section 1 Overview............................................................................................... 1 1.1 Overview................................................................................................................................ 1 1.2 Internal Block Diagrams ........................................................................................................ 5 1.3 Pin Description....................................................................................................................... 6 1.3.1 Pin Arrangements...................................................................................................... 6 1.3.2 Pin Functions in Each Operating Mode .................................................................... 8 1.3.3 Pin Functions .......................................................................................................... 12 Section 2 CPU..................................................................................................... 17 2.1 ...
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Program Execution State......................................................................................... 61 2.8.5 Bus-Released State ................................................................................................. 61 2.8.6 Power-Down State .................................................................................................. 61 2.9 Basic Timing........................................................................................................................ 62 2.9.1 Overview................................................................................................................. 62 2.9.2 On-Chip Memory (ROM, RAM) ............................................................................ 62 2.9.3 On-Chip Supporting Module Access Timing ......................................................... 64 2.9.4 External Address ...
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Interrupts .............................................................................................................................. 87 4.5 Trap Instruction.................................................................................................................... 88 4.6 Stack Status after Exception Handling................................................................................. 89 4.7 Notes on Use of the Stack .................................................................................................... 90 Section 5 Interrupt Controller ............................................................................. 91 5.1 Overview.............................................................................................................................. 91 5.1.1 Features................................................................................................................... 91 5.1.2 Block Diagram ........................................................................................................ ...
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Section 6 Bus Controller....................................................................................119 6.1 Overview............................................................................................................................ 119 6.1.1 Features................................................................................................................. 119 6.1.2 Block Diagram...................................................................................................... 120 6.1.3 Pin Configuration.................................................................................................. 121 6.1.4 Register Configuration.......................................................................................... 122 6.2 Register Descriptions ......................................................................................................... 123 6.2.1 Bus Width Control Register (ABWCR)................................................................ 123 6.2.2 Access State Control Register (ASTCR) ...
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Operation .............................................................................................................. 162 6.8.3 Bus Transfer Timing ............................................................................................. 163 6.8.4 External Bus Release Usage Note......................................................................... 163 6.9 Resets and the Bus Controller ............................................................................................ 164 6.10 External Module Expansion Function................................................................................ 164 6.10.1 Overview............................................................................................................... 164 6.10.2 Pin Configuration.................................................................................................. 165 6.10.3 Register ...
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Repeat Mode ......................................................................................................... 217 7.5.5 Normal Mode........................................................................................................ 221 7.5.6 Block Transfer Mode ............................................................................................ 224 7.5.7 DMAC Activation Sources ................................................................................... 230 7.5.8 Basic DMAC Bus Cycles...................................................................................... 232 7.5.9 DMAC Bus Cycles (Dual Address Mode)............................................................ 233 7.5.10 DMAC Multi-Channel Operation ......................................................................... ...
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Examples of Use of the DTC ................................................................................ 278 8.4 Interrupts ............................................................................................................................ 280 8.5 Usage Notes ....................................................................................................................... 280 Section 9 I/O Ports ............................................................................................ 281 9.1 Overview............................................................................................................................ 281 9.2 Port 1 .............................................................................................................................. 285 9.2.1 Overview............................................................................................................... 285 9.2.2 Register Configuration.......................................................................................... 286 9.2.3 ...
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Port D .............................................................................................................................. 337 9.10.1 Overview............................................................................................................... 337 9.10.2 Register Configuration.......................................................................................... 338 9.10.3 Pin Functions in Each Mode ................................................................................. 340 9.10.4 MOS Input Pull-Up Function................................................................................ 341 9.11 Port E .............................................................................................................................. 342 9.11.1 Overview............................................................................................................... 342 9.11.2 Register Configuration.......................................................................................... 343 9.11.3 Pin ...
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Overview............................................................................................................... 391 10.4.2 Basic Functions..................................................................................................... 392 10.4.3 Synchronous Operation......................................................................................... 399 10.4.4 Buffer Operation ................................................................................................... 401 10.4.5 PWM Modes ......................................................................................................... 405 10.4.6 Phase Counting Mode ........................................................................................... 411 10.5 Interrupts ............................................................................................................................ 416 10.5.1 Interrupt Sources and Priorities............................................................................. 416 10.5.2 DTC and ...
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Pin Configuration.................................................................................................. 457 12.1.4 Register Configuration.......................................................................................... 458 12.2 Register Descriptions ......................................................................................................... 459 12.2.1 Receive Shift Register (RSR) ............................................................................... 459 12.2.2 Receive Data Register (RDR) ............................................................................... 459 12.2.3 Transmit Shift Register (TSR) .............................................................................. 460 12.2.4 Transmit Data Register (TDR).............................................................................. 460 ...
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Usage Note......................................................................................................................... 541 Section 15 ROM ............................................................................................... 543 15.1 Overview............................................................................................................................ 543 15.1.1 Block Diagram ...................................................................................................... 543 15.1.2 Register Configuration.......................................................................................... 544 15.2 Register Descriptions ......................................................................................................... 544 15.2.1 Mode Control Register (MDCR) .......................................................................... 544 15.3 Operation............................................................................................................................ 545 15.4 Overview of Flash ...
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Socket Adapter Pin Correspondence Diagram...................................................... 583 15.13.2 Programmer Mode Operation ............................................................................... 585 15.13.3 Memory Read Mode ............................................................................................. 586 15.13.4 Auto-Program Mode ............................................................................................. 590 15.13.5 Auto-Erase Mode.................................................................................................. 592 15.13.6 Status Read Mode ................................................................................................. 594 15.13.7 Status Polling ........................................................................................................ 595 15.13.8 ...
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Module Stop Mode ............................................................................................... 626 17.5.2 Usage Notes .......................................................................................................... 628 17.6 Software Standby Mode..................................................................................................... 628 17.6.1 Software Standby Mode........................................................................................ 628 17.6.2 Clearing Software Standby Mode ......................................................................... 629 17.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.... 629 17.6.4 ...
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C.2 Port 3 Block Diagrams....................................................................................................... 831 C.3 Port 4 Block Diagram ........................................................................................................ 835 C.4 Port 7 Block Diagrams....................................................................................................... 836 C.5 Port 9 Block Diagram ........................................................................................................ 841 C.6 Port A Block Diagrams ...................................................................................................... 842 C.7 Port B Block Diagram........................................................................................................ 846 C.8 ...
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Figures Section 1 Overview Figure 1.1 H8S/2214 Group Internal Block Diagram................................................................... 5 Figure 1.2 H8S/2214 Group Pin Arrangement (TFP-100B, TFP-100BV, TFP-100G, TFP-100GV: Top View)................................. 6 Figure 1.3 H8S/2214 Group Pin Arrangement (BP-112, BP-112V, TBP-112A, TBP-112AV: Top View) ......................................... 7 Section ...
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Figure 4.3 Reset Sequence (Mode 4).......................................................................................... 85 Figure 4.4 Interrupt Sources and Number of Interrupts.............................................................. 87 Figure 4.5 Stack Status after Exception Handling (Normal Modes: Not available in the H8S/2214)...................................................... 89 Figure 4.6 Stack Status after Exception Handling (Advanced Modes) ...
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Figure 6.23 On-Chip ROM Valid Extended Mode (Mode 6) Address Map............................... 172 Section 7 DMA Controller Figure 7.1 Block Diagram of DMAC ....................................................................................... 174 Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)............................. 204 Figure 7.3 Operation in ...
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Figure 8.6 Memory Mapping in Normal Mode ........................................................................ 269 Figure 8.7 Memory Mapping in Repeat Mode ......................................................................... 270 Figure 8.8 Memory Mapping in Block Transfer Mode ............................................................ 272 Figure 8.9 Chain Transfer Memory Map.................................................................................. 273 Figure 8.10 DTC Operation Timing ...
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Figure 10.11 Example of Toggle Output Operation ..................................................................... 396 Figure 10.12 Example of Input Capture Operation Setting Procedure ......................................... 397 Figure 10.13 Example of Input Capture Operation....................................................................... 398 Figure 10.14 Example of Synchronous Operation Setting Procedure .......................................... 399 Figure 10.15 ...
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Figure 10.52 Contention between Overflow and Counter Clearing ............................................. 435 Figure 10.53 Contention between TCNT Write and Overflow .................................................... 436 Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of WDT.......................................................................................... 438 Figure 11.2 Format of Data Written to TCNT ...
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Figure 12.22 Example of SCI Operation in Transmission............................................................ 514 Figure 12.23 Sample Serial Reception Flowchart ........................................................................ 515 Figure 12.24 Example of SCI Operation in Reception ................................................................. 516 Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ........ 517 ...
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Figure 15.20 Socket Adapter Pin Correspondence Diagram ........................................................ 584 Figure 15.21 Timing Waveforms for Memory Read after Memory Write ................................... 587 Figure 15.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode..... 588 Figure 15.23 CE and OE ...
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Figure 18.10 Burst ROM Access Timing/Two-State Access ....................................................... 651 Figure 18.11 External Bus Release Timing .................................................................................. 652 Figure 18.12 I/O Port Input/Output Timing.................................................................................. 654 Figure 18.13 TPU Input/Output Timing ....................................................................................... 654 Figure 18.14 TPU Clock Input Timing......................................................................................... 654 Figure 18.15 ...
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Figure C.27 Port F Block Diagram (Pin PF2) ............................................................................. 852 Figure C.28 Port F Block Diagram (Pin PF3) ............................................................................. 853 Figure C.29 Port F Block Diagram (Pins PF4 to PF6) ................................................................ 854 Figure C.30 Port F Block Diagram (Pin PF7) ...
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Tables Section 1 Overview Table 1.1 Overview ..................................................................................................................... 2 Table 1.2 Pin Functions in Each Operating Mode....................................................................... 8 Table 1.3 Pin Functions............................................................................................................. 12 Section 2 CPU Table 2.1 Instruction Classification........................................................................................... 34 Table 2.2 Combinations of Instructions and Addressing Modes............................................... 35 ...
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Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses ..................... 113 Table 5.11 Interrupt Source Selection and Clearing Control .................................................... 118 Section 6 Bus Controller Table 6.1 Bus Controller Pins ................................................................................................. 121 Table 6.2 Bus Controller Registers ......................................................................................... ...
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Section 9 I/O Ports Table 9.1 H8S/2214 Group Port Functions ............................................................................. 282 Table 9.2 Port 1 Registers ....................................................................................................... 286 Table 9.3 Port 1 Pin Functions ................................................................................................ 288 Table 9.4 Port 3 Registers ....................................................................................................... 297 Table 9.5 Port 3 Pin Functions ...
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Table 10.12 Interrupt Sources and DMA Controller (DMAC) and Data Transfer (DTC) Activation................................................................................................................ 416 Section 11 Watchdog Timer (WDT) Table 11.1 WDT Registers........................................................................................................ 439 Section 12 Serial Communication Interface (SCI) Table 12.1 SCI Pins................................................................................................................... 457 Table 12.2 SCI Registers........................................................................................................... 458 ...
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Table 15.10 Hardware Protection................................................................................................ 576 Table 15.11 Software Protection ................................................................................................. 577 Table 15.12 Programmer Mode Pin Settings............................................................................... 583 Table 15.13 Settings for Various Operating Modes In Programmer Mode................................. 585 Table 15.14 Programmer Mode Commands................................................................................ 586 Table 15.15 AC Characteristics in ...
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Table 18.10 DMAC Timing ........................................................................................................ 656 Table 18.11 D/A Conversion Characteristics .............................................................................. 657 Table 18.12 Flash Memory Characteristics................................................................................. 658 Appendix A Instruction Set Table A.1 Data Transfer Instructions ....................................................................................... 663 Table A.2 Arithmetic Instructions............................................................................................ 666 Table A.3 Logical Instructions................................................................................................. 670 ...
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Overview The H8S/2214 Group is a microcomputer (MCU: microcomputer unit), built around the H8S/2000 CPU, employing Renesas' proprietary architecture, and equipped with the on-chip peripheral functions necessary for system configuration. The H8S/2000 CPU has an internal 32-bit architecture, is ...
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Section 1 Overview Table 1.1 Overview Item Specification • CPU General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate 16 MHz ...
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Item Specification • Data transfer Can be activated by internal interrupt or software controller (DTC) • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc. • Request ...
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Section 1 Overview Item Specification Operating modes Four MCU operating modes CPU Operating Mode Mode 4 Advanced On-chip ROM disabled Clock pulse Clock pulse generators generator • System clock pulse generator MHz On-chip duty ...
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Internal Block Diagrams Figures 1.1 shows internal block diagram of the H8S/2214. MD2 MD1 MD0 EXTAL XTAL STBY RES NMI FWE PF7 /φ PF6 /AS PF5 /RD PF4 /HWR PF3 /LWR/IRQ3 PF2 /WAIT PF1 /BACK PF0 /BREQ/IRQ2 PG4 /CS0 ...
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Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangements Figures 1.2 and 1.3 show the pin arrangements of the H8S/2214. P30/TxD0 76 77 P31/RxD0 P32/SCK0/IRQ4 78 P33/TxD1 79 P34/RxD1 80 P35/SCK1/IRQ5 81 P36/EXIRQ7 82 P77 83 P76/EXMSTP 84 P75/EXMS 85 ...
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PF1/ PF4/HWR 11 Reserve BACK PF2/ P30/TxD0 Reserve 10 WAIT P32/ PF0/ BREQ/ SCK0/ P33/TxD1 9 IRQ4 IRQ2 P35/ P36/ SCK1/ 8 P34/RxD1 P31/RxD1 PF6/AS EXIRQ7 IRQ5 P74/ P75/ P76/ MRES/ 7 EXMS EXMSTP EXDTCE P72/ P71/ P73/ TEND0/ DREQ1/ ...
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Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2214 Group in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No. TFP-100B, BP-112, TFP-100BV, BP-112V, ...
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Pin No. TFP-100B, BP-112, TFP-100BV, BP-112V, TFP-100G, TBP-112A, TFP-100GV TBP-112AV Mode PB3/A11 26 K2 PB4/A12 27 L2 PB5/A13 28 H4 PB6/A14 29 K3 PB7/A15 30 L3 PA0/A16 31 J4 PA1/A17/TxD2 32 K4 PA2/A18/RxD2 33 L4 PA3/A19/SCK2 34 ...
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Section 1 Overview Pin No. TFP-100B, BP-112, TFP-100BV, BP-112V, TFP-100G, TBP-112A, TFP-100GV TBP-112AV Mode 4 50 L10 P42/EXIRQ2 51 K10 P41/EXIRQ1 52 K11 P40/EXIRQ0 53 H8 Vref 54 J10 AVCC 55 J11 MD0 56 H9 MD1 57 H10 Reserve 58 ...
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Pin No. TFP-100B, BP-112, TFP-100BV, BP-112V, TFP-100G, TBP-112A, TFP-100GV TBP-112AV Mode P33/TxD1 80 C8 P34/RxD1 81 B8 P35/SCK1/IRQ5 82 A8 P36/EXIRQ7 83 D7 P77 84 C7 P76/EXMSTP 85 A7 P75/EXMS 86 B7 P74/MRES/ EXDTCE 87 C6 P73/TEND1/CS7 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2214. Table 1.3 Pin Functions Type Symbol Power VCC VSS Clock XTAL EXTAL φ Operating MD2 to mode control MD0 Rev.4.00 Sep. 18, 2008 Page 12 ...
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Type Symbol RES System control MRES STBY BREQ BACK FWE Interrupts NMI IRQ7 to IRQ0 Address bus A23 to A0 Data bus D15 to D0 CS7 to Bus control CS0 AS RD HWR LWR WAIT EXIRQ7 to External EXIRQ0 expansion ...
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Section 1 Overview Type Symbol EXDTC External expansion EXMSTP DREQ1, DMA controller DREQ0 (DMAC) TEND1, TEND0 16-bit timer- TCLKD to pulse unit (TPU) TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 Serial TxD2, communication TxD1, interface (SCI) TxD0 RxD2, ...
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Type Symbol I/O ports P17 to P10 P36 to P30 P47 to P40 P77 to P70 P96 PA3 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG4 to PG0 RESERVE RESERVE ...
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Section 1 Overview Rev.4.00 Sep. 18, 2008 Page 16 of 872 REJ09B0189-0400 ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate ⎯ 8/16/32-bit register-register add/subtract : 62.5 ns ⎯ 8 × 8-bit register-register multiply ⎯ 16 ÷ 8-bit register-register divide ⎯ ...
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There are also differences in the address space, CCR and EXR register functions, power-down state, etc., depending on the product. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More ...
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Section 2 CPU • Higher speed ⎯ Basic instructions execute twice as fast 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal * and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a ...
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Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. (d) Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 ...
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Section 2 CPU (e) Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they ...
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Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored ...
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Section 2 CPU (e) Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in ...
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Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. Note ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. SP (ER7) 2.4.3 Control Registers The ...
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Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ...
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Section 2 CPU The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.12 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes — @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 @aa:24 @aa:16 @aa:8 @–ERn/@ERn+ @(d:32,ERn) @(d:16,ERn) ...
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Section 2 CPU — @@aa:8 @(d:16,PC) @(d:8,PC) @aa:32 @aa:24 @aa:16 @aa:8 @–ERn/@ERn+ @(d:32,ERn) @(d:16,ERn) @ERn Rn #xx Rev.4.00 Sep. 18, 2008 Page 36 of 872 REJ09B0189-0400 ...
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Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source General register * ...
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Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM * 2 STM * 2 Rev.4.00 Sep. 18, 2008 Page 38 of 872 REJ09B0189-0400 Size * 1 Function (EAs) → Rd, ...
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Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Size * 1 Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two ...
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Section 2 CPU Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS * 3 Rev.4.00 Sep. 18, 2008 Page 40 of 872 REJ09B0189-0400 Size * 1 Function Rd ÷ Rs → Rd B/W Performs signed division on data in ...
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Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size * 1 Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a ...
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Section 2 CPU Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Rev.4.00 Sep. 18, 2008 Page 42 of 872 REJ09B0189-0400 Size * 1 Function 1 → (<bit-No.> of <EAd>) B Sets a specified bit in ...
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Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Size * 1 Function C ⊕ (<bit-No.> of <EAd>) → Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores ...
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Section 2 CPU Type Instruction Branch Bcc instructions JMP BSR JSR RTS Rev.4.00 Sep. 18, 2008 Page 44 of 872 REJ09B0189-0400 Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed ...
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Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Size * 1 Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. — Causes a transition to a power-down state. (EAs) → CCR, ...
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Section 2 CPU Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. The STM/LDM instructions may only be used with the ER0 to ER6 registers. 3. ...
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Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc field). Figure 2.13 ...
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Section 2 CPU (3) Effective Address Extension Eight, 16 bits specifying immediate data, an absolute address displacement. (4) Condition Field Specifies the branching condition of Bcc instructions. 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, ...
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Table 2.4 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect (1) Register ...
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Section 2 CPU • Register indirect with pre-decrement—@-ERn The value subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. ...
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Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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Section 2 CPU Specified Branch address by @aa:8 (a) Normal Mode* Note: * Not available in the H8S/2214 Group. Figure 2.14 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, ...
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Table 2.6 Effective Address Calculation Section 2 CPU Rev.4.00 Sep. 18, 2008 Page 53 of 872 REJ09B0189-0400 ...
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Section 2 CPU Rev.4.00 Sep. 18, 2008 Page 54 of 872 REJ09B0189-0400 ...
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Section 2 CPU Rev.4.00 Sep. 18, 2008 Page 55 of 872 REJ09B0189-0400 ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.15 shows a diagram of the processing states. Figure 2.16 ...
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End of bus request Bus-released state End of exception handling Exception-handling state MRES = high Manual reset state * 1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the power-on reset state occurs whenever ...
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Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the ...
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Reset Exception Handling After the RES or MRES pin has gone low and the reset state has been entered, reset exception handling starts when RES or MRES goes high again. The CPU enters the power-on reset state when the ...
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Section 2 CPU Normal mode * 2 SP CCR CCR * PC (16 bits) (a) Interrupt control mode 0 Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. Ignored when returning. 2. Not available in ...
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Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than ...
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Section 2 CPU modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol φ. The period ...
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Bus cycle φ Address bus Unchanged AS RD HWR, LWR Data bus High-impedance state Figure 2.19 Pin States during On-Chip Memory Access T 1 High High High Rev.4.00 Sep. 18, 2008 Page 63 of 872 Section 2 CPU REJ09B0189-0400 ...
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Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.20 ...
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Address bus AS RD HWR, LWR Data bus Figure 2.21 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a ...
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Section 2 CPU 2.10.2 STM/LDM Instruction Usage With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot be used as a register that allows save (STM) or restore (LDM) operation. With a ...
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Example: Using the BCLR instruction to clear only P14 in the port 1 P1DDR register. The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins. Reading this register is invalid. When read, ...
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Section 2 CPU The bit manipulation operation is performed on this value that was read. In this example, bit 4 will be cleared for H'F8. P17 I/O Output Output P1DDR 1 After bit 1 manipulation After the bit manipulation operation, ...
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Write data to the work area Write the work area data to the register that includes write-only bits Access the work area data (data transfer and bit manipulation instructions can be used) Write the work area data to the register ...
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Section 2 CPU To switch P14 from being an output pin to being an input pin, we must change the value of P1DDR bit 4 from (H'F0 → H'E0). Here, were execute a BCLR instruction for RAM0. ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2214 Group has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width ...
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Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2214 Group can be used only in modes This means that the mode pins must be set to select ...
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MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. 3.2.2 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : ...
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Section 3 MCU Operating Modes Bit 2—Manual Reset Select (MRESE): Enables or disables the MRES pin. Table 3.3 shows the relationship between the RES and MRES pin values and type of reset. For details of resets, see section 4.2, Resets. ...
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Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D ...
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Section 3 MCU Operating Modes The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16- bit access is designated by the bus controller for any area, the bus mode ...
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Pin Functions in Each Operating Mode The pin functions of ports 1, and vary depending on the operating mode. Table 3.4 shows their functions in each operating mode. Table 3.4 Pin Functions in Each Mode Port ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFB000 Reserved area* H'FFC000 On-chip RAM* External address H'FFEFC0 space H'FFF800 Internal I/O registers H'FFFF40 External address space H'FFFF60 Internal ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Direct transition External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and the H8S/2214 enters the reset state. A reset initializes the internal state of ...
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A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. When the MRES pin is used, MRES pin input must be enabled by setting the MRESE bit to ...
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Section 4 Exception Handling φ RES, MRES Internal address bus Internal read signal Internal write signal Internal data bus (1) Reset exception handling vector address (for a power-on reset, (1) = H'0000; for a manual reset, (1) = H'0002) (2) ...
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RES, MRES Address bus RD HWR, LWR D15 to D0 (1) (3) Reset exception handling vector address (for a power-on reset, (1) = H'000000, (3) = H'000002; for a manual reset, (1) = H'000004, (3) = H'000006) (2) (4) ...
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Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0), eight external expansion sources (EXIRQ7 to EXIRQ0), and 31 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the ...
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Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address ...
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Stack Status after Exception Handling Figures 4.5 and 4.6 show the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. ...
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Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2214 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2214 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes ⎯ Any of two interrupt control modes can be ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request SWDTEND to TEI2 ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests EXIRQ7 to External expansion EXIRQ0 interrupt sources 7 ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Priority Registers (IPRA to IPRD, IPRF, IPRG, IPRJ, IPRK, IPRM) Bit : 7 — Initial value : 0 R/W : — The IPR registers are nine 8-bit readable/writable registers that ...
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Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA Initial value : 0 R/W : R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA Initial value : 0 R/W : R/W The ISCR registers are ...
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Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/W : R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (53 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be ...
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Section 5 Interrupt Controller IRQnSCA, IRQnSCB Edge/level detection circuit IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQn Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Note ...
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Internal Interrupts There are 31 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. ...
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Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI0 (interval timer) TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input ...
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Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) DEND0A (channel 0/channel 0A transfer end) ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2214 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and ...
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Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. ...
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Section 5 Interrupt Controller The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, ...
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Section 5 Interrupt Controller IRQ0 Yes Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Rev.4.00 Sep. 18, 2008 Page 108 of 872 REJ09B0189-0400 Program execution status Interrupt generated? Yes Yes NMI Yes No IRQ1 ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.6 shows a ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Rev.4.00 Sep. 18, 2008 Page 110 of 872 REJ09B0189-0400 Program execution status No Interrupt generated? Yes ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2214 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed ...
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Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch Branch address read Stack manipulation 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable ...
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Section 5 Interrupt Controller φ Internal address bus Internal write signal TGIEA TGFA TGIOA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After ...
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Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With ...
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Section 5 Interrupt Controller 5.6 DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to ...
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Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source DMAC inputs activation factor directly to each channel. The activation factors for each channel of DMAC are selected by DTF3 to ...
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Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTC DTA DTCE Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source ...
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Section 6 Bus Controller 6.1 Overview The H8S/2214 Group has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK WAIT Legend: ABWCR: Bus width control register ASTCR: Access state control register BCRH: Bus ...
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Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write LWR Low write CS0 to Chip select CS7 WAIT Wait ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 Modes Initial value : R/W Mode 4 Initial value : R/W ABWCR is an 8-bit readable/writable register that ...
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Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) Bit : 7 AST7 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal ...
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Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bus Control Register H (BCRH) Bit : 7 ICIS1 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH ...
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Section 6 Bus Controller Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM Description 0 Area 0 is basic bus interface 1 Area 0 is burst ROM interface Bit 4—Burst ...
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Bus Control Register L (BCRL) Bit : 7 BRLE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. ...
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Section 6 Bus Controller 6.2.6 Pin Function Control Register (PFCR) Bit : 7 — Modes 4 and 5 Initial value : 0 Modes 6 and 7 Initial value : 0 R/W : R/W PFCR is an 8-bit readable/writable register that ...
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Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 ...
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Section 6 Bus Controller 6.3 Overview of Bus Control 6.3.1 Area Divisions In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 2-Mbyte units, and performs bus control for external space ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2214 Group memory ...
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Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and ...
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Section 6 Bus Controller 6.3.5 Chip Select Signals The H8S/2214 Group can output chip select signals (CS0 to CS7) to areas the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows ...