R5F64189DFD#U0 Renesas Electronics America, R5F64189DFD#U0 Datasheet - Page 25

• Manufacturer Part Number: R5F64189DFD#U0
• Description: MCU 1M+8K FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/118r

Specifications of R5F64189DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 63K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/118 Group
REJ03B0255-0110
Jun 23, 2010
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.8.1
2.1.8.2
2.1.8.3
2.1.8.4
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into
R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).
These 32-bit registers have functions similar to data registers. They are also used for address register
indirect addressing and address register relative addressing.
This 32-bit register is used for SB relative addressing.
This 32-bit register is used for FB relative addressing.
This 32-bit counter indicates the address of the instruction to be executed next.
This 32-bit register indicates the start address of a relocatable vector table.
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP).
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for
details.
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.
This 32-bit register indicates the CPU status.
This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic
logic unit (ALU).
This flag is only for debugging. Only set this bit to 0.
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
General Purpose Registers
Data Registers (R2R0, R3R1, R6R4, and R7R5)
Address Registers (A0, A1, A2, and A3)
Static Base Register (SB)
Frame Base Register (FB)
Program Counter (PC)
Interrupt Vector Table Base Register (INTB)
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Flag Register (FLG)
Carry Flag (C flag)
Debug Flag (D flag)
Zero Flag (Z flag)
Sign Flag (S flag)
Rev.1.10
2. Central Processing Unit (CPU)
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