MC9S12XDP512MAG Freescale Semiconductor, MC9S12XDP512MAG Datasheet - Page 335
MC9S12XDP512MAG
Manufacturer Part Number
MC9S12XDP512MAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDP512MAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (24-ch x 10-bit)
Package
144LQFP
Family Name
HCS12
Maximum Speed
40 MHz
For Use With
DEMO9S12XDT512E - BOARD DEMO FOR MC9S12XDT512EVB9S12XDP512E - BOARD DEMO FOR MC9S12XDP512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
7.3.2.18
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents
are respectively the high and low byte of the PACB.
Freescale Semiconductor
Reset
Reset
Reset
W
W
W
R
R
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
PACNT7
PACNT7
Pulse Accumulators Count Registers (PACN1 and PACN0)
0
0
0
7
7
7
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
PACNT6
PACNT6
Figure 7-38. Pulse Accumulators Count Register 2 (PACN2)
Figure 7-39. Pulse Accumulators Count Register 1 (PACN1)
Figure 7-40. Pulse Accumulators Count Register 0 (PACN0)
0
0
0
6
6
6
PACNT5
PACNT5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
5
5
5
PACNT4
PACNT4
NOTE
0
0
0
4
4
4
PACNT3
PACNT3
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
0
3
3
3
PACNT2
PACNT2
0
0
0
2
2
2
PACNT1(9)
PACNT1
PACNT1
0
0
0
1
1
1
PACNT0(8)
PACNT0
PACNT0
0
0
0
0
0
0
335
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