MC9S12H256VFVE Freescale Semiconductor, MC9S12H256VFVE Datasheet
MC9S12H256VFVE
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MC9S12H256VFVE Summary of contents
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... MC9S12H256 Device User Guide V01.20 Covers also MC9S12H128 Original Release Date: 29 SEP 2000 Revised: 28 JUL 2008 Freescale Semiconductor Inc. MC9S12H256 Device User Guide — V01.20 1 ...
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Revision History Version Revision Effective Number Date Date 07 MAR 03 APR V01.00 2001 2001 10 MAI 10 MAY V01.01 2001 2001 14 MAY 14 MAY V01.02 2001 2001 30 MAY 30 MAY V01.03 2001 2001 11 JUN 11 JUN ...
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Version Revision Effective Number Date Date 11 OCT 11 OCT V01.11 2001 2001 07 NOV 07 NOV V01.12 2001 2001 08 MAR 08 MAR V01.13 2002 2002 16 DEC 16 DEC V01.14 2002 2002 31 MAR 31 MAR V01.15 2003 ...
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MC9S12H256 Device User Guide — V01.20 4 ...
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Section 1 Introduction 1.1 Overview ...
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MC9S12H256 Device User Guide — V01.20 2.3.24 PM5 / TXCAN1 — Port M I/O Pin ...
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Overview ...
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MC9S12H256 Device User Guide — V01.20 Section 13 Pulse Width Modulator (PWM) Block Description Section 14 Flash EEPROM 256K Block Description Section 15 EEPROM 4K Block Description Section 16 RAM Block Description Section 17 Liquid Crystal Display Driver (LCD) Block ...
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A.2.3 ATD accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MC9S12H256 Device User Guide — V01.20 10 ...
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Figure 1-1 MC9S12H256 Block Diagram ...
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MC9S12H256 Device User Guide — V01.20 12 ...
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Table 0-1 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MC9S12H256 Device User Guide — V01.20 14 ...
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Preface The Device User Guide provides information about the MC9S12H256 and MC9S12H128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes ...
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MC9S12H256 Device User Guide — V01.20 16 ...
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Section 1 Introduction 1.1 Overview The MC9S12H256 microcontroller unit (MCU 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, ...
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MC9S12H256 Device User Guide — V01.20 – BDM (Background Debug Mode) • CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) • 8-bit and 4-bit ports with interrupt functionality – Digital filtering – Programmable rising ...
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Inter-Integrated Circuit interface (IIC) • Liquid Crystal Display driver with variable input voltage – Configurable for frontplanes and 4 backplanes or general purpose input or output – 5 modes of operation allow for different display sizes ...
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MC9S12H256 Device User Guide — V01.20 • Stop Mode • Pseudo Stop Mode • Wait Mode 1.4 Block Diagram Figure 1 block diagram of the MC9S12H256 device. 20 ...
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VDDR VDD1 VSS1,VSS2 256k Bytes Flash EEPROM 4k Bytes EEPROM 12K Bytes RAM Single-wire Background BKGD Debug Module XFC VDDPLL Clock and VSSPLL Reset PLL Generation EXTAL XTAL Module RESET TEST PE0 XIRQ PE1 IRQ PE4 ECLK PE5 MODA PE6 ...
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MC9S12H256 Device User Guide — V01.20 Figure 1 block diagram of the MC9S12H128 device. 22 ...
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VDDR VDD1 VSS1,VSS2 128k Bytes Flash EEPROM 2k Bytes EEPROM 6K Bytes RAM Single-wire Background BKGD Debug Module XFC VDDPLL Clock and VSSPLL Reset PLL Generation EXTAL XTAL Module RESET TEST PE0 XIRQ PE1 IRQ PE4 ECLK PE5 MODA PE6 ...
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MC9S12H256 Device User Guide — V01.20 1.5 Device Memory Map 24 ...
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MC9S12H256 Device User Guide — V01.20 25 ...
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MC9S12H256 Device User Guide — V01.20 Table 1-1 and Figure 1-3 show the device memory map of the MC9S12H256. Table 1-1 Device Memory Map MC9S12H256 Address $0000 – $0017 $0018 – $0019 $001A – $001B $001C – $001F $0020 – ...
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EXT $C000 $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED* SINGLE CHIP Figure 1-3 MC9S12H256 Memory Map Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128. Table 1-2 Device Memory Map MC9S12H128 ...
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MC9S12H256 Device User Guide — V01.20 Table 1-2 Device Memory Map MC9S12H128 Address $00C8 – $00CF $00D0 – $00D7 $00D8 – $00DF $00E0 – $00FF $0100 – $010F $0110 – $011B $011C – $011F $0120 – $0137 $0140 – $017F ...
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EXT $C000 $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED* SINGLE CHIP Figure 1-4 MC9S12H128 Memory Map MC9S12H256 Device User Guide — V01.20 $0000 1K Register Space $03FF Mappable to any 2K Boundary $0000 2K Bytes ...
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MC9S12H256 Device User Guide — V01.20 1.5.1 Detailed Register Map $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: Read: $0004 Reserved Write: Read: $0005 Reserved Write: Read: ...
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INT map (Core User Guide) Address Name Bit 7 Read: $0015 ITCR Write: Read: $0016 ITEST INTE Write: $0017 - $0017 MMC map (Core User Guide) Address Name Bit 7 Read: ...
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MC9S12H256 Device User Guide — V01.20 $0020 - $0027 Address Name Read: $0020 - Reserved $0027 Write: $0028 - $002F Address Name Read: $0028 BKPCT0 Write: Read: $0029 BKPCT1 Write: Read: $002A BKP0X Write: Read: $002B BKP0H Write: Read: $002C ...
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CRG (Clock and Reset Generator) Address Name Bit 7 Read: $0034 SYNR Write: Read: $0035 REFDV Write: Read: CTFLG $0036 TEST ONLY Write: Read: $0037 CRGFLG RTIF Write: Read: $0038 CRGINT RTIE Write: Read: $0039 CLKSEL PLLSEL ...
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MC9S12H256 Device User Guide — V01.20 $0040 - $006F Address Name Read: $004A TCTL3 Write: Read: $004B TCTL4 Write: Read: $004C TIE Write: Read: $004D TSCR2 Write: Read: $004E TFLG1 Write: Read: $004F TFLG2 Write: Read: $0050 TC0 (hi) Write: ...
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TIM (Timer 16 Bit 8 Channels) Address Name Bit 7 Read: $0063 PACNT (lo) Bit 7 Write: Read: $0064 Reserved Write: Read: $0065 Reserved Write: Read: $0066 Reserved Write: Read: $0067 Reserved Write: Read: $0068 Reserved Write: ...
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MC9S12H256 Device User Guide — V01.20 $0080 - $00AF Address Name Read: $0086 ATDSTAT0 Write: Read: $0087 Reserved Write: Read: $0088 ATDTEST0 Write: Read: $0089 ATDTEST1 Write: Read: CCF15 $008A ATDSTAT2 Write: Read: $008B ATDSTAT1 Write: Read: $008C ATDDIEN0 Write: ...
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ATD (Analog to Digital Converter 10 Bit 16 Channel) Address Name Bit 7 Read: Bit7 $009F ATDDR7L Write: Read: Bit15 $00A0 ATDDR8H Write: Read: Bit7 $00A1 ATDDR8L Write: Read: Bit15 $00A2 ATDDR9H Write: Read: Bit7 $00A3 ATDDR9L ...
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MC9S12H256 Device User Guide — V01.20 $00C0 - $00C7 Address Name Read: $00C2 IBCR Write: Read: $00C3 IBSR Write: Read: $00C4 IBDR Write: Read: $00C5 Reserved Write: Read: $00C6 Reserved Write: Read: $00C7 Reserved Write: $00C8 - $00CF Address Name ...
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SCI1 (Asynchronous Serial Interface) only on MC9S12H256 Address Name Bit 7 Read: $00D5 SCI1SR2 Write: Read: R8 $00D6 SCI1DRH Write: Read: R7 $00D7 SCI1DRL Write: T7 $00D8 - $00DF SPI (Serial Peripheral Interface) Address Name Bit 7 ...
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MC9S12H256 Device User Guide — V01.20 $00E0 - $00FF Address Name Read: $00E9 PWMSCLB Write: Read: PWMSCNTA $00EA Test Only Write: PWMSCNTB Read: $00EB Test Only Write: Read: $00EC PWMCNT0 Write: Read: $00ED PWMCNT1 Write: Read: $00EE PWMCNT2 Write: Read: ...
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Flash Control Register (fts256k) Address Name Bit 7 Read: FDIVLD $0100 FCLKDIV Write: Read: KEYEN $0101 FSEC Write: Read: $0102 Reserved Write: Read: $0103 FCNFG CBEIE Write: Read: $0104 FPROT FPOPEN Write: Read: $0105 FSTAT CBEIF Write: ...
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MC9S12H256 Device User Guide — V01.20 $0110 - $011B Address Name Read: $0119 EADDRLO Write: Read: $011A EDATAHI Write: Read: $011B EDATALO Write: $011C - $011F Address Name Read: $011C - Reserved $011F Write: $0120 - $0137 Address Name Read: ...
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LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes) Address Name Bit 7 Read: $0130 LCDRAM8 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 Write: Read: $0131 LCDRAM9 FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0 Write: Read: ...
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MC9S12H256 Device User Guide — V01.20 $0140 - $017F Address Name Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 $014F CAN0TXERR Write: Read: $0150 - CAN0IDAR0 - $0153 CAN0IDAR3 Write: $0154 - CAN0IDMR0 - Read: $0157 CAN0IDMR3 Write: Read: ...
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Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Extended ID Read: ID14 CAN0TIDR2 Write: $0172 Standard ID Read: Write: Extended ID Read: ID6 CAN0TIDR3 Write: $0173 Standard ID Read: Write: $0174- CAN0TDSR0 - Read: ...
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MC9S12H256 Device User Guide — V01.20 $0180 - $01BF Address Name Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 $018E CAN1RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 $018F CAN1TXERR Write: $0190 - CAN1IDAR0 - Read: ...
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Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Extended ID Read: ID20 CAN1TIDR1 Write: $01B1 Standard ID Read: ID2 Write: Extended ID Read: ID14 CAN1TIDR2 Write: $01B2 Standard ID Read: Write: Extended ID Read: ...
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MC9S12H256 Device User Guide — V01.20 $01C0 - $01FF Address Name Read: $01CC Reserved Write: Read: $01CD Reserved Write: Read: $01CE Reserved Write: Read: $01CF Reserved Write: Read: $01D0 MCCC0 Write: Read: $01D1 MCCC1 Write: Read: $01D2 MCCC2 Write: Read: ...
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MC (Motor Controller 10bit 12 channels) Address Name Bit 7 Read: $01E5 MCDC2 (lo) D7 Write: Read: $01E6 MCDC3 (hi) Write: Read: $01E7 MCDC3 (lo) D7 Write: Read: $01E8 MCDC4 (hi) Write: Read: $01E9 MCDC4 (lo) D7 ...
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MC9S12H256 Device User Guide — V01.20 $01C0 - $01FF Address Name Read: $01FD Reserved Write: Read: $01FE Reserved Write: Read: $01FF Reserved Write: $0200 - $027F Address Name Read: $0200 PTT Write: Read: $0201 PTIT Write: Read: $0202 DDRT Write: ...
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PIM (Port Integration Module) Address Name Bit 7 Read: $0213 RDRM Write: Read: $0214 PERM Write: Read: $0215 PPSM Write: Read: $0216 WOMM Write: Read: $0217 Reserved Write: Read: $0218 PTP Write: Read: $0219 PTIP Write: Read: ...
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MC9S12H256 Device User Guide — V01.20 $0200 - $027F Address Name Read: $022C PERJ Write: Read: $022D PPSJ Write: Read: $022E PIEJ Write: Read: $022F PIFJ Write: Read: $0230 PTL Write: Read: $0231 PTIL Write: Read: $0232 DDRL Write: Read: ...
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Address Name Read: $0245 PPSV Write: Read: $0246 Reserved Write: Read: $0247 Reserved Write: Read: $0248 PTW Write: Read: $0249 PTIW Write: Read: $024A DDRW Write: Read: $024B SRRW Write: Read: $024C PERW Write: Read: $024D PPSW ...
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MC9S12H256 Device User Guide — V01.20 NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - ...
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Section 2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals built from the signal description sections of the Block User Guides of ...
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MC9S12H256 Device User Guide — V01.20 1 M0C0M/PU0 2 M0C0P/PU1 3 M0C1M/PU2 4 M0C1P/PU3 5 VDDM1 6 VSSM1 7 M1C0M/PU4 M1C0P/PU5 8 9 M1C1M/PU6 M1C1P/PU7 10 11 M2C0M/PV0 M2C0P/PV1 12 M2C1M/PV2 13 M2C1P/PV3 14 VDDM2 15 VSSM2 16 M3C0M/PV4 17 ...
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M0C0M/PU0 1 M0C0P/PU1 2 M0C1M/PU2 3 M0C1P/PU3 4 VDDM1 5 VSSM1 6 M1C0M/PU4 7 M1C0P/PU5 8 M1C1M/PU6 9 M1C1P/PU7 10 KWH0/PH0 11 KWH1/PH1 12 KWH2/PH2 13 KWH3/PH3 14 M2C0M/PV0 15 M2C0P/PV1 16 M2C1M/PV2 17 M2C1P/PV3 18 VDDM2 19 VSSM2 20 ...
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MC9S12H256 Device User Guide — V01.20 2.2 Signal Properties Summary Table 2-1 summarizes all pin functions. NOTE: Bold entries determine pins not available on 112-pin LQFP. Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 EXTAL — ...
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Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 PM5 TXCAN1 — PM4 RXCAN1 — PM3 TXCAN0 — PM2 RXCAN0 — PM1 SCL — PM0 SDA — PP[5:2] PWM[5:2] — PP[1:0] PWM[1:0] — PS7 SS — PS6 ...
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MC9S12H256 Device User Guide — V01.20 2.3 Detailed Signal Descriptions 2.3.1 EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. ...
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PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins PB7-PB0 are general purpose input or output pins. They can be configured as frontplane segment driver outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, ...
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MC9S12H256 Device User Guide — V01.20 2.3.15 PE2 / FP20 / R/W — Port E I/O Pin 2 PE2 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP20 of the LCD ...
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FreescalePL[7:4] / FP[31:28] — Port L I/O Pins [7:4] PL7-PL4 are general purpose input or output pins. They can be configured as frontplane segment driver outputs FP31-FP28 of the LCD module. NOTE: These pins are not available in the ...
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MC9S12H256 Device User Guide — V01.20 2.3.30 PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2] PP5-PP2 are general purpose input or output pins. They can be configured as Pulse Width Modulator (PWM) channel outputs PWM5-PWM2. NOTE: These pins are ...
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PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general purpose input or output pin. It can be configured as transmit pin TXD0 of the Serial Communication Interface 0 (SCI0). 2.3.39 PS0 / RXD0 — Port ...
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MC9S12H256 Device User Guide — V01.20 2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0] PV3-PV0 are general purpose input or output pins. They can be configured as high current PWM output pins which can be ...
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VDD1, VSS1, VSS2 — Core Power Pins VDD1, VSS1 and VSS2 are the core power and ground pins and related to the voltage regulator output. These pins serve as connection points for filter capacitors. VSS1 and VSS2 are internally ...
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MC9S12H256 Device User Guide — V01.20 68 ...
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Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block ...
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Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12H256. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device. 4.2 Modes of ...
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MC9S12H256 Device User Guide — V01.20 even located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe ...
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If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin ...
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MC9S12H256 Device User Guide — V01. internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, ...
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Special Single-Chip Mode When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the ...
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MC9S12H256 Device User Guide — V01.20 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: • Protection of the contents of FLASH, • Protection of the ...
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FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and ...
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Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of ...
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MC9S12H256 Device User Guide — V01.20 Table 5-1 Reset and Interrupt Vector Table Vector Address Interrupt Source $FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 CRG Self Clock Mode $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, ...
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Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset. MC9S12H256 Device User Guide — V01.20 81 ...
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Section 6 HCS12 Core Block Description Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), breakpoint module (BKP) ...
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MC9S12H256 Device User Guide — V01.20 There are two Serial Communications Interfaces (SCI0 and SCI1) implemented on the MC9S12H256 device and one SCI (SCI0) on MC9S12H128. Consult the SCI Block User Guide for information about each Serial Communications Interface module. ...
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There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult the MSCAN Block User Guide for information on each MSCAN. Section 19 PWM Motor Control (MC) Block Description Consult the MC_10B12C Block User Guide for information ...
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MC9S12H256 Device User Guide — V01.20 21.2 Recommended PCB layout Figure 21-1 LQFP112 recommended PCB layout VDDM1 C7 VSSM1 VDDM2 C6 VSSM2 VDDM3 C5 VSSM3 VDDR/ VDDX2 86 VDDX1 Q1 VSSPLL VDDPLL R1 VSS1 C1 VDD1 VDDA C2 VSSA ...
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Figure 21-2 LQFP144 recommended PCB layout VDDM1 C7 VSSM1 VDDM2 C6 VSSM2 VDDM3 C5 VSSM3 VDDR/ VDDX2 MC9S12H256 Device User Guide — V01.20 VDDX1 Q1 VSSPLL VDDPLL R1 VSS1 C1 VDD1 VDDA C2 VSSA 87 ...
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MC9S12H256 Device User Guide — V01.20 Component The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must ...
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Appendix A Electrical Characteristics A.1 General This supplement contains the most accurate electrical information for the MC9S12H256 and MC9S12H128 microcontroller available at the time of publication. This introduction is intended to give an overview on several common topics like power ...
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MC9S12H256 Device User Guide — V01.20 VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX1, VDDX2, VDDM as well ...
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MCU is not consuming power; e. system clock is present clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. ...
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MC9S12H256 Device User Guide — V01.20 5. Those pins are internally clamped This pin is clamped low to V A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for ...
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A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device ( with regards to the ...
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MC9S12H256 Device User Guide — V01. Junction Temperature Ambient Temperature Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ C/W] JA The total power dissipation can ...
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MC9S12H256 Device User Guide — V01.20 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage 2 P Input Low Voltage 3 C Input Hysteresis Input Leakage Current except PU, PV, PW (pins ...
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Conditions are shown in Table A-4 unless otherwise noted 16 D Input Capacitance 4 Injection current 17 T Single Pin limit Total Device Limit. Sum of all injected currents 18 P Port H, J Interrupt Input Pulse filtered 19 P ...
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MC9S12H256 Device User Guide — V01.20 given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise ...
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A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results ...
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MC9S12H256 Device User Guide — V01.20 operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This ...
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A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted – ...
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MC9S12H256 Device User Guide — V01.20 DNL LSB V i–1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Figure ...
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A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. ...
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MC9S12H256 Device User Guide — V01.20 A.3.1.3 Sector Erase Erasing a 512 byte Flash sector byte EEPROM sector takes: The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The ...
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The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table A-12 NVM Reliability Characteristics ...
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A.4 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.4.1 Startup Table A-13 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can ...
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MC9S12H256 Device User Guide — V01.20 A.4.1.4 Stop Recovery Out of STOP the controller can be woken external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. A.4.1.5 Pseudo ...
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XCLKS =1 during reset A.4.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.4.3.1 XFC Component Selection This section ...
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MC9S12H256 Device User Guide — V01.20 The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, C typical values are 50. = 0.9 ensures a good transient response. f < ...
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The relative deviation its maximum for one clock period, and decreases towards zero for larger nom number of clock periods (N). Defining the jitter as For ...
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MC9S12H256 Device User Guide — V01.20 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Conditions are shown in Table A-4 unless otherwise ...
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A.5 MSCAN Table A-16 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P MSCAN Wake-up dominant pulse filtered 2 P MSCAN Wake-up dominant pulse pass MC9S12H256 Device User Guide — V01.20 ...
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A.6 SPI A.6.1 Master Mode Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17 (OUTPUT) 2 SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT MISO 2 MSB ...
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MC9S12H256 Device User Guide — V01. (OUTPUT SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT) 5 MISO MSB IN (INPUT) 9 MOSI PORT DATA MASTER MSB OUT (OUTPUT configured as output 2. LSBF ...
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A.6.2 Slave Mode Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18. SS (INPUT) SCK (CPOL 0) (INPUT) 2 SCK (CPOL 1) (INPUT) 7 MISO MSB OUT SLAVE (OUTPUT MOSI ...
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MC9S12H256 Device User Guide — V01.20 Table A-18 SPI Slave Mode Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs Num C Rating 1 P Operating Frequency P SCK Period t = ...
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A.7 LCD_32F4B Table A.7-19 LCD_32F4B Driver Electrical Characteristics Characteristic LCD Supply Voltage LCD Output Impedance(BP[3:0],FP[31:0]) for outputs to charge to higher voltage level GND LCD Output Current (BP[3:0],FP[31:0]) for outputs to discharge to lower voltage level 2 ...
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A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-20. All major bus signals are included in the diagram. While both a data write ...
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MC9S12H256 Device User Guide — V01.20 ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 IPIPO0 IPIPO1, PE6,5 Figure ...
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Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 1 P Frequency of operation (E-clock Cycle time 3 D Pulse width, E low Pulse width, ...
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MC9S12H256 Device User Guide — V01.20 Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 32 D NOACC hold time 33 D IPIPO[1:0] delay time D IPIPO[1:0] valid time to ...
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Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12H256 and MC9S12H128 packages. MC9S12H256 Device User Guide — V01.20 125 ...
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MC9S12H256 Device User Guide — V01.20 B.2 112-pin LQFP package 0. PIN 1 112 IDENT 1 VIEW 0.050 C1 VIEW AB Figure B-1 112-pin LQFP mechanical ...
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B.3 144-pin LQFP package 0. PIN 1 144 IDENT PLATING BASE D METAL 0. SECTION J1-J1 (ROTATED 90 ) 144 ...
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User Guide End Sheet MC9S12H256 Device User Guide — V01.20 129 ...
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