MC9S12H256VFVE Freescale Semiconductor, MC9S12H256VFVE Datasheet - Page 107
![IC MCU 256K FLASH 16MHZ 144-LQFP](/photos/12/30/123001/mc9s12h256vfve_sml.jpg)
MC9S12H256VFVE
Manufacturer Part Number
MC9S12H256VFVE
Description
IC MCU 256K FLASH 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12H256VFVER.pdf
(130 pages)
Specifications of MC9S12H256VFVE
Core Processor
HCS12
Core Size
16-Bit
Speed
16MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
99
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
115
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12H256VFVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12H256VFVER
Manufacturer:
Freescale
Quantity:
551
Company:
Part Number:
MC9S12H256VFVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
A.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.4.1 Startup
Table A-13 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
A.4.1.1 POR
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
2
3
4
5
6
D Reset input pulse width, minimum input time
D Startup from Reset
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
T POR release level
T POR assert level
PORR
and the assert level V
CQOUT
Rating
Table A-13 Startup Characteristics
no valid oscillation is detected, the MCU will start using the internal self
PORA
are derived from the VDD supply. They are also valid
uposc
Symbol
PW
PW
V
V
n
t
.
PORR
PORA
WRS
RST
RSTL
RSTL
IRQ
MC9S12H256 Device User Guide — V01.20
the CRG module generates an internal
Min
0.97
192
20
2
Typ
Max
2.07
196
14
Unit
n
t
t
osc
ns
cyc
osc
V
V
107