M30626FJPFP#U7C Renesas Electronics America, M30626FJPFP#U7C Datasheet - Page 72

IC M16C/62P MCU FLASH 100QFP

M30626FJPFP#U7C

Manufacturer Part Number
M30626FJPFP#U7C
Description
IC M16C/62P MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPFP#U7C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ03B0001-0241
Switching Characteristics
(V
Figure 5.12
CC1
Table 5.46
NOTES:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
th(WR-DB)
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
d(BCLK-HLDA)
Symbol
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
3. This standard value shows the timing when the output is off, and
= V
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
by a circuit of the right figure.
For example, when V
of output ”L” level is
CC2
Jan 10, 2006
----------------------- - 40 ns
f BCLK
----------------------- - 10 ns
f BCLK
0.5x10
0.5x10
t = − CR X ln (1 − V
t = − 30pF X 1k Ω X In(1 − 0.2V
(
(
= 6.7ns.
= 3V, V
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
9
9
Ports P0 to P14 Measurement Circuit
Memory Expansion and Microprocessor Modes (for setting with no wait)
)
)
SS
[
[
= 0V, at T
]
]
OL
OL
Page 70 of 96
/ V
= 0.2V
CC2
)
f(BCLK) is 12.5MHz or less.
CC2
opr
CC2
, C = 30pF, R = 1k Ω , hold time
Parameter
= −20 to 85°C / −40 to 85°C unless otherwise specified)
/ V
CC2
)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
(3)
(3)
30pF
See
Figure 5.12
(NOTE 2)
(NOTE 1)
(NOTE 2)
V
DBi
Min.
CC1
− 4
5. Electrical Characteristics
4
0
4
0
0
4
Standard
=V
Max.
30
30
25
30
30
40
40
CC2
C
R
=3V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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