MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 70

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4-30
IF BREAKPOINT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
IF BREAKPOINT INSTRUCTION EXECUTED AND
IF BKPT PIN ASSERTED AND
IF BERR ASSERTED:
IF BKPT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
IF BKPT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
1) INITIATE HARDWARE BREAKPOINT PROCESSING
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
7) ASSERT AS AND DS
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
7) ASSERT AS AND DS
1) SET R/W TO READ
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
1) SET R/W TO READ
4) PLACE ALL ONES ON ADDR[4:2]
5) SET T-BIT (ADDR1) TO ONE
6) SET SIZE TO WORD
2) SET FUNCTION CODE TO CPU SPACE
2) SET FUNCTION CODE TO CPU SPACE
2) CONTINUE PROCESSING
1) CONTINUE PROCESSING
DSACK IS ASSERTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
DSACK IS ASSERTED:
3) GO TO (A)
2) GO TO (A)
2) GO TO (B)
1) LATCH DATA
2) NEGATE AS AND DS
1) NEGATE AS AND DS
1) NEGATE AS AND DS
(A)
ACKNOWLEDGE BREAKPOINT
CPU32
Figure 4-12 Breakpoint Operation Flowchart
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
(B)
Go to: www.freescale.com
BREAKPOINT OPERATION FLOW
IF BKPT INSTRUCTION EXECUTED:
IF BKPT ASSERTED:
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1) NEGATE DSACK or BERR
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACK
1) ASSERT DSACK
OR:
OR:
PERIPHERAL
USER’S MANUAL
MC68332
1110A