MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 41
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MC68332GVEH25
Manufacturer Part Number
MC68332GVEH25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332GVEH25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
132-QFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Controller Family/series
68K
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
25MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
15
Number Of Timers
16
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68332GVEH25
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC68332GVEH25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3.8 Interrupts
3.8.1 Interrupt Acknowledge and Arbitration
MC68332
MC68332TS/D
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
system integration module, and a device or module requesting interrupt service.
The CPU32 provides for eight levels of interrupt priority (0–7), seven automatic interrupt vectors, and
200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the in-
terrupt priority (IP) field in the status register. The CPU32 handles interrupts as a type of asynchronous
exception.
Interrupt recognition is based on the states of interrupt request signals iIRQ[7:1] and the IP mask value.
Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the
highest priority.
The IP field consists of three bits. Binary values %000 to %111 provide eight priority masks. Masks pre-
vent an interrupt request of a priority less than or equal to the mask value (except for IRQ7) from being
recognized and processed. When IP contains %000, no interrupt is masked. During exception process-
ing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request
lines are connected internally by means of a wired NOR — simultaneous requests of differing priority
can be made. Internal assertion of an interrupt request signal does not affect the logic state of the cor-
responding MCU pin.
External interrupt requests are routed to the CPU via the external bus interface and SIM interrupt control
logic. The CPU treats external interrupt requests as though they come from the SIM.
External IRQ[6:1] are active-low level-sensitive inputs. External IRQ7 is an active-low transition-sensi-
tive input. IRQ7 requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent
redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is as-
serted, and each time the priority mask changes from %111 to a lower number whileIRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending re-
quests are processed at instruction boundaries or when exception processing of higher-priority excep-
tions is complete.
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the
CPU does not recognize the occurrence of the request in any way.
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU detects
one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a
CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the inter-
rupt source. The mask value also serves two purposes: it is latched into the CCR IP field in order to
When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent
mode selection. Once the output drivers change state, the MCU must be powered down and re-
started before normal operation can resume.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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