MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 53
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MC68332GVEH25
Manufacturer Part Number
MC68332GVEH25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332GVEH25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
132-QFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Controller Family/series
68K
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
25MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
15
Number Of Timers
16
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68332GVEH25
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC68332GVEH25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.1.2 Input Capture/Input Transition Counter (ITC)
5.1.3 Output Compare (OC)
5.1.4 Pulse-Width Modulation (PWM)
5.1.5 Synchronized Pulse-Width Modulation (SPWM)
5.1.6 Period Measurement with Additional Transition Detect (PMA)
MC68332
MC68332TS/D
one of three ways:
Any channel of the TPU can capture the value of a specified TCR upon the occurrence of each transition
or specified number of transitions, and then generate an interrupt request to notify the CPU. A channel
can perform input captures continually, or a channel can detect a single transition or specified number
of transitions, then cease channel activity until reinitialization. After each transition or specified number
of transitions, the channel can generate a link to a sequential block of up to eight channels. The user
specifies a starting channel of the block and the number of channels within the block. The generation
of links depends on the mode of operation. In addition, after each transition or specified number of tran-
sitions, one byte of the parameter RAM (at an address specified by channel parameter) can be incre-
mented and used as a flag to notify another channel of a transition.
The output compare function generates a rising edge, falling edge, or a toggle of the previous edge in
This algorithm generates a 50% duty-cycle continuous square wave with each high/low time equal to
the calculated OFFSET. Due to offset calculation, there is an initial link time before continuous pulse
generation begins.
The TPU can generate a pulse-width modulation waveform with any duty cycle from zero to 100% (with-
in the resolution and latency capability of the TPU). To define the PWM, the CPU provides one param-
eter that indicates the period and another parameter that indicates the high time. Updates to one or both
of these parameters can direct the waveform change to take effect immediately, or coherently beginning
at the next low-to-high transition of the pin.
The TPU generates a PWM waveform in which the CPU can change the period and/or high time at any
time. When synchronized to a time function on a second channel, the synchronized PWM low-to-high
transitions have a time relationship to transitions on the second channel.
This function and the following function are used primarily in toothed-wheel speed-sensing applications,
such as monitoring rotational speed of an engine. The period measurement with additional transition
detect function allows for a special-purpose 23-bit period measurement. It can detect the occurrence of
an additional transition (caused by an extra tooth on the sensed wheel) indicated by a period measure-
ment that is less than a programmable ratio of the previous period measurement.
Once detected, this condition can be counted and compared to a programmable number of additional
transitions detected before TCR2 is reset to $FFFF. Alternatively, a byte at an address specified by a
channel parameter can be read and used as a flag. A nonzero value of the flag indicates that TCR2 is
to be reset to $FFFF once the next additional transition is detected.
1. Immediately upon CPU initiation, thereby generating a pulse with a length equal to a program-
2. At a programmable delay time from a user-specified time.
3. Continuously. Upon receiving a link from a channel, OC references, without CPU interaction, a
mable delay time.
specifiable period and calculates an offset:
where Ratio is a parameter supplied by the user.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Offset = Period Ratio
MOTOROLA
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