M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 254
M30879FLGP#U3
Manufacturer Part Number
M30879FLGP#U3
Description
IC M32C/87 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Specifications of M30879FLGP#U3
Core Size
16/32-Bit
Program Memory Size
1MB (1M x 8)
Core Processor
M32C/80
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
M32C
No. Of I/o's
85
Ram Memory Size
48KB
Cpu Speed
32MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30879FLGP#U3M30879FLGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 230 of 587
Figure 17.14
17.1.1.1 CLK Polarity
As shown in figure 17.14, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial
clock.
(1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input
The above applies under the following conditions:
NOTES:
falling edge and receive data input at the rising edge of the serial clock )
at the falling edge of the serial clock)
- UFORM bit in the UiC0 register is set to 0 (LSB first)
- UiLCH bit in the UiC1 register is set to 0 (not inverted).
1. The CLKi pin output level is "H" when no transmit and receive operation is in progress.
2. The CLKi pin output level is "L" when no transmit and receive operation is in progress.
CLKi
TXDi
RXDi
CLKi
TXDi
RXDi
Serial Clock Polarity
"H"
"H"
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
"L"
"L"
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
17. Serial Interfaces (UART0 to UART4)
D6
D6
D6
D6
D7
D7
D7
D7
(note 1)
(note 2)
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