M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 241
M30879FLFP#U3
Manufacturer Part Number
M30879FLFP#U3
Description
IC M32C/87 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M30879FLFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 217 of 587
Figure 17.3
UARTi Special Mode Register (i = 0 to 4)
b7
b6 b5 b4
NOTES:
1. These bits are used in I
2. The BBS bit is set to 0 by writing a 0. Writing a 1 has no effect.
3. These bits are used in IE mode.
4. UART0: Timer A3 underflow signal, UART1: Timer A4 underflow signal,
5. The SCLKDIV bit is used in GCI mode.
6. Refer to the note for the SU1HIM bit in the UiSMR2 register.
UART2: Timer A0 underflow signal, UART3: Timer A3 underflow signal,
UART4: Timer A4 underflow signal.
b3
0
b2
U0SMR to U4SMR Registers
b1
b0
Bit Symbol
SCLKDIV
ABSCS
ACSE
IICM
ABC
BBS
SSS
Symbol
U0SMR to U2SMR
U3SMR, U4SMR
(b3)
2
−
C mode.
I
Arbitration lost detect flag
control bit
Bus busy flag
Reserved bit
Bus conflict detect
sampling clock select bit
Auto clear function select
bit for transmit enable bit
Transmit start condition
select bit
Clock division synchronous
bit
2
C mode select bit
(5,6)
(3)
(1)
Bit Name
(1, 2)
Address
0367h, 02E7h, 0337h
0327h, 02F7h
(3)
(3)
0 : Other than I
1 : I
0: Updated per bit
1: Updated per byte
0: Stop condition detected (bus is free)
1: Start condition detected (bus is busy)
Set to 0
0: Rising edge of serial clock
1: Timer Aj underflow (j = 0, 3, 4)
0: No auto clear function
1: Auto cleared when bus conflict occurs
0 : Not related to RXDi
1 : Synchronized with RXDi
0: External clock not divided
1: External clock divided by 2
2
C mode
17. Serial Interfaces (UART0 to UART4)
2
C mode
Function
(4)
After Reset
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
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