M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 313
M30879FLFP#U3
Manufacturer Part Number
M30879FLFP#U3
Description
IC M32C/87 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M30879FLFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 289 of 587
Figure 17.52
(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)
(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)
Internal transmit
clock
TE bit in the
UiC1 register
TI bit in the UiC1
register
CTSi input
TXDi output
TXEPT bit in the
UiC0 register
UiTR bit in the
IIOjIR register
Internal transmit
clock
TE bit in the
UiC1 register
TI bit in the UiC1
register
TXDi output
TXEPT bit in the
UiC0 register
UiTR bit in the
IIOjIR register
The above applies under the following conditions:
The above applies under the following conditions:
TC =
j = 1 when i = 5, j = 10 when i = 6
NOTE:
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
- UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used)
- U56CON register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed)
- UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits)
- UiC0 register: CRD bit = 1 (CTS function disabled)
- U56CON register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register)
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
16(m + 1)
fj
Transmit Operation in UART mode
“H”
“L”
“H”
“L”
“H”
“L”
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
fj: f1, f8, f2n
fEXT: clock input to the CLKi pin when the external clock is selected
m: setting value of the UiBRG register (00h to FFh)
Start bit
Start bit
ST
ST
Write data to UiTB register
Write data to UiTB register
(1)
TC
TC
D0
D0
Set to 0 by an interrupt request acknowledgement or by a program
, fEXT
D1 D2 D3 D4 D5 D6
D1 D2 D3 D4 D5 D6
Transfer data from UiTB register to UARTi transmit shift register
Parity bit
D7
D7
Transfer data from UiTB register to UARTi transmit shift register
D8
P
Stop bit
Set to 0 by an interrupt request acknowledgement or by a program
Stop bits
SP
SP
SP
ST
Transmission stops because TE = 0
D0 D1 D2 D3 D4 D5 D6
ST
D0 D1 D2 D3 D4 D5 D6
17. Serial Interfaces (UART5 and UART6)
D7
P
D7
SP
D8
SP
SP
ST
D0
ST
D0
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