ATTINY13A-SF Atmel, ATTINY13A-SF Datasheet - Page 15
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ATTINY13A-SF
Manufacturer Part Number
ATTINY13A-SF
Description
IC MCU AVR 1K FLASH 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SF
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY13A-SFR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
5. Memories
5.1
5.2
8126E–AVR–07/10
In-System Reprogrammable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the ATtiny13A. The AVR architecture has two
main memory spaces, the Data memory and the Program memory space. In addition, the
ATtiny13A features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
The ATtiny13A contains 1K byte On-chip In-System Reprogrammable Flash memory for pro-
gram storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x
16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13A Pro-
gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations.
“Memory Programming” on page 103
loading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 5-1.
Figure 5-2 on page 16
The lower 160 Data memory locations address both the Register File, the I/O memory and the
internal data SRAM. The first 32 locations address the Register File, the next 64 locations the
standard I/O memory, and the last 64 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
12.
Program Memory Map
shows how the ATtiny13A SRAM Memory is organized.
Program Memory
contains a detailed description on Flash data serial down-
0x01FF
0x0000
“Instruction Execution Tim-
15