ATTINY13A-SF Atmel, ATTINY13A-SF Datasheet - Page 75
![IC MCU AVR 1K FLASH 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY13A-SF
Manufacturer Part Number
ATTINY13A-SF
Description
IC MCU AVR 1K FLASH 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SF
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY13A-SFR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
11.9.4
11.9.5
11.9.6
8126E–AVR–07/10
OCR0A – Output Compare Register A
OCR0B – Output Compare Register B
TIMSK0 – Timer/Counter Interrupt Mask Register
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
• Bits 7:4, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13A and will always read as zero.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
Bit
0x36
Read/Write
Initial Value
Bit
0x29
Read/Write
Initial Value
Bit
0x39
Read/Write
Initial Value
R/W
R/W
R
7
–
0
7
0
7
0
R/W
R/W
R
6
–
0
6
0
6
0
R/W
R/W
R
5
–
0
5
0
5
0
R/W
R/W
R
4
–
0
4
0
4
0
OCR0A[7:0]
OCR0B[7:0]
OCIE0B
R/W
R/W
R/W
3
0
3
0
3
0
OCIE0A
R/W
R/W
R/W
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R
0
0
0
0
0
–
0
TIMSK0
OCR0A
OCR0B
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