ATTINY24A-MUR Atmel, ATTINY24A-MUR Datasheet - Page 37

• Manufacturer Part Number: ATTINY24A-MUR
• Description: MCU AVR 2KB FLASH 20MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.2
8183C–AVR–03/11
PRR – Power Reduction Register
• Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between available sleep modes, as shown in
Table 7-2.
Note:
• Bit 2 – BODSE: BOD Sleep Enable
The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD
disable is controlled by a timed sequence.
This bit is unused in devices where software BOD disable has not been implemented and will
read as zero in those devices.
The Power Reduction Register provides a method to reduce power consumption by allowing
peripheral clock signals to be disabled.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
• Bit 2 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
• Bit 1 – PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When
waking up the USI again, the USI should be re initialized to ensure proper operation.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
The analog comparator cannot be used when the ADC is shut down.
Bit
0x00 (0x20)
Read/Write
Initial Value
SM1
1. Only recommended with external crystal or resonator selected as clock source
0
0
1
1
Sleep Mode Select
R
7
–
0
SM0
R
6
–
0
0
1
0
1
R
5
–
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Standby
R
4
–
0
(1)
PRTIM1
R/W
3
0
ATtiny24A/44A/84A
PRTIM0
R/W
Table
2
0
7-2.
PRUSI
R/W
1
0
PRADC
R/W
0
0
PRR
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