ATTINY2313A-SUR Atmel, ATTINY2313A-SUR Datasheet - Page 22

• Manufacturer Part Number: ATTINY2313A-SUR
• Description: MCU AVR 2KB FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

5.5.2
5.5.3
22
ATtiny2313A/4313
EEDR – EEPROM Data Register
EECR – EEPROM Control Register
• Bits 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny2313A/4313. For compatibil-
ity with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny2313A/4313 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in
Table 5-1.
When EEPE is set any write to EEPMn will be ignored. During reset, the EEPMn bits will be
reset to 0b00 unless the EEPROM is busy programming.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when Non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
EEPM1
0
0
1
1
EEPM0
EEPROM Programming Mode Bits and Programming Times
EEDR7
0
1
0
1
R/W
R
7
0
7
–
0
Programming Time
EEDR6
R/W
R
6
0
6
–
0
3.4 ms
1.8 ms
1.8 ms
–
EEDR5
EEPM1
R/W
R/W
5
0
5
X
EEDR4
EEPM0
R/W
R/W
X
4
0
4
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
EEDR3
EERIE
R/W
R/W
3
0
3
0
EEMPE
EEDR2
R/W
R/W
2
0
2
0
EEDR1
EEPE
R/W
R/W
X
1
0
1
Table
EEDR0
EERE
R/W
R/W
5-1.
0
0
0
0
8246A–AVR–11/09
EEDR
EECR