ATTINY261A-SU Atmel, ATTINY261A-SU Datasheet
ATTINY261A-SU
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ATTINY261A-SU Summary of contents
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... MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Power Consumption at 1MHz, 1.8V, 25°C – Active: 200 µA – Power-Down Mode: 0.1 µA ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny261A ATtiny461A ATtiny861A Preliminary 8197B–AVR–01/10 ...
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... Pin Configurations Figure 1-1. Pinout ATtiny261A/461A/861A (MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 (OC1B/PCINT11) PB3 (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 Note: To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board. ...
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Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 AVCC Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC), the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port A. ...
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... Overview ATtiny261A/461A/861A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the devices achieve throughputs approaching 1 MIPS per MHz allowing the system designer to opti- mize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The ATtiny261A/461A/861A AVR is supported by a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. ...
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... Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATtiny261A/461A/861A 6 8197B–AVR–01/10 ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. ATtiny261A/461A/861A 8 8197B–AVR–01/10 ...
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SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control ...
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... The registers R26:R31 have some added functions to their general purpose usage. These regis- ters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATtiny261A/461A/861A 10 below shows the structure of the 32 general purpose working registers in the CPU. ...
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Figure 4-3. X-register Y-register Z-register In different addressing modes these address registers function as automatic increment and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, local variables ...
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... Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 4-5. Total Execution Time Register Operands Fetch ALU Operation Execute ATtiny261A/461A/861A SP15 SP14 SP13 SP12 ...
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Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny261A/461A/861A 14 ; store SREG value ; disable interrupts during timed sequence ...
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... Memories This section describes the different memories of the ATtiny261A/461A/861A. The AVR architec- ture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny261A/461A/861A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data SRAM in the ATtiny261A/461A/861A are all accessible through all these addressing modes. The Register File is described in Figure 5-2. ...
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EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...
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... Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: ATtiny261A/461A/861A 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; See “Code Examples” on page 6. “OSCCAL – Oscillator Calibration Register” on ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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... Bit 0 – EEAR8: EEPROM Address This is the most significant EEPROM address bit of ATtiny861A. In devices with less EEPROM, i.e. ATtiny261A/ATtiny461A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed ...
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... Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny461A. In devices with less EEPROM, i.e. ATtiny261A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...
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... The user should poll the EEPE bit before starting the read opera- tion write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. 5.5.5 GPIOR2 – General Purpose I/O Register 2 Bit 0x0C (0x2C) Read/Write Initial Value ATtiny261A/461A/861A 22 EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms ...
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GPIOR1 – General Purpose I/O Register 1 Bit 0x0B (0x2B) Read/Write Initial Value 5.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x0A (0x2A) Read/Write Initial Value 8197B–AVR–01/ MSB R/W R/W R/W R ...
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... The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. ATtiny261A/461A/861A 24 presents the principal clock systems and their distribution. All of the clocks need not 34 ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 6.1.4 ADC Clock – clk ADC The ADC is provided with a dedicated ...
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... The internal PLL generates a clock signal with a frequency eight times higher than the source input. The PLL uses the output of the internal 8 MHz oscillator as source and the default setting generates a fast peripheral clock signal of 64 MHz. ATtiny261A/461A/861A 26 Number of Watchdog Oscillator Cycles ...
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The fast peripheral clock, clk prescaled version of the PLL output, clk a detailed illustration on the PLL clock system. Figure 6-3. XTAL1 XTAL2 The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit ...
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... Notes: When this oscillator is selected, start-up times are determined by SUT fuses as shown in 6-7. Table 6-7. SUT1 ( Note: ATtiny261A/461A/861A 28 Table 6-5. Start-up Times for the PLLCK Start-up Time from Power Down Power-On-Reset (V 14CK + 1K (1024 14CK + 16K (16384 14CK + 1K (1024 14CK + 16K (16384 and “ ...
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... Table 6-9. Table 6-9. SUT1 Notes: Table 6-10. ATtiny261A/461A/861A 8197B–AVR–01/10 “OSCCAL – Oscillator Calibration Register” on page “Calibration Byte” on page Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power- down and Power-save the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + ensure programming mode can be entered ...
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... The operating mode is selected by fuses CKSEL3:1 as shown in The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in 6-12. Table 6-12. CKSEL0 ATtiny261A/461A/861A 30 Crystal Oscillator Connections C2 C1 Table 6-11. For ceramic resonators, the capacitor values given by Crystal Oscillator Operating Modes ...
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Table 6-12. CKSEL0 Notes: 6.2.7 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal Oscillator running at 8 ...
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... CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved and will always read as zero. ATtiny261A/461A/861A ...
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Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to ...
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... CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk allowing the other clocks to run. ATtiny261A/461A/861A 34 presents the different clock systems and their distribution. The figure is Active Clock Domains and Wake-up Sources in Different Sleep Modes ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting ...
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... If the reference is kept on in sleep mode, the output can be used immediately. Refer to age Reference” on page 42 ATtiny261A/461A/861A 36 “PRR – Power Reduction Register” on page for examples. In all other sleep modes, the clock is already “ ...
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Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the ...
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... USI again, the USI should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. Also analog comparator needs this clock. ATtiny261A/461A/861A 38 Sleep Mode Select SM0 ...
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System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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... Reset Sources The ATtiny261A/461A/861A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. ...
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External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see ate a reset, even if the clock is not running. Shorter pulses are ...
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... Timer” on page 42 Figure 8-6. 8.3 Internal Voltage Reference ATtiny261A/461A/861A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The bandgap voltage varies with supply voltage and temperature, as can be seen in page 217 ...
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The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out ...
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... WDT_off(void) { _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; } Note: ATtiny261A/461A/861A 44 r16, (0<<WDRF) MCUSR, r16 r16, WDTCSR See “Code Examples” on page 6. 8197B–AVR–01/10 ...
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Register Description 8.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved ...
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... To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: • Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler and 0 ATtiny261A/461A/861A 46 Watchdog Timer Configuration WDIE Watchdog Timer State ...
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The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3. Table 8-3. WDP3 ...
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... Interrupts ATtiny261A/461A/861A. For a general explanation of the AVR interrupt handling, refer to and Interrupt Handling” on page 9.1 Interrupt Vectors Interrupt vectors of ATtiny261A/461A/861A are described in Table 9-1. Vector No the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. ...
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Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 ... 9.2 External Interrupts The External Interrupts are triggered by the INT0 ...
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... Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU ATtiny261A/461A/861A 50 24. ...
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Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall- ing edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. ...
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... If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny261A/461A/861A ...
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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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... Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to ATtiny261A/461A/861A 54 (1) SLEEP ...
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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...
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... In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK INSTRUCTIONS SYNC LATCH ATtiny261A/461A/861A 56 XXX PINxn r17 Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of ...
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Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. ATtiny261A/461A/861A 58 See “Code Examples” on page 6 ...
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Figure 10-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: 8197B–AVR–01/10 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATtiny261A/461A/861A 60 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...
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Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. • Port A, Bit 7- ADC6/AIN0/PCINT7 • ADC6: Analog to Digital Converter, Channel 6 • AIN0: Analog Comparator Input. Configure the port ...
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... ADC0: Analog to Digital Converter, Channel 0. • DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. • SDA: Two-wire mode Serial Interface Data. • PCINT0: Pin Change Interrupt source 0. ATtiny261A/461A/861A 62 8197B–AVR–01/10 ...
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Table 10-4 shown in Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8197B–AVR–01/10 and Table 10-5 relate the ...
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... When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. ATtiny261A/461A/861A 64 Port B Pins Alternate Functions Port Pin ...
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ADC10: ADC input Channel 10. Note that ADC input channel 10 uses analog power. • PCINT15: Pin Change Interrupt source 15. • Port B, Bit 6 - ADC9/ T0/ INT0/ PCINT14 • ADC9: ADC input Channel 9. Note that ...
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... Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: ATtiny261A/461A/861A 66 and Table 10-8 relate the alternate functions of Port B to the overriding signals Figure 10-5 on page 59. Overriding Signals for Alternate Functions in PB7:PB4 PB7/RESET/ dW/ADC10/ PB6/ADC9/T0/ PCINT15 INT0/PCINT14 (1) RSTDISBL • ...
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Table 10-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 10.3 Register Description 10.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this ...
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... Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 10.3.7 PINB – Port B Input Pins Address Bit 0x16 (0x36) Read/Write Initial Value ATtiny261A/461A/861A PINA7 PINA6 PINA5 PINA4 R/W R/W R/W R/W N/A ...
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... The general operation of Timer/Counter0 is described in 8/16-bit mode. A simplified block dia- gram of the 8/16-bit Timer/Counter is shown in including I/O bits and I/O pins, are shown in bold. For actual placement of I/O pins, refer to out ATtiny261A/461A/861A” on page in the “Register Description” on page Figure 11-1. 8-/16-bit Timer/Counter Block Diagram 11 ...
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... The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. See Figure 11-2 ATtiny261A/461A/861A 70 must be followed. Table 11-1 are also used extensively throughout the document. Definitions ...
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Figure 11-2. Prescaler for Timer/Counter0 clk I/O PSR0 T0 Note: The prescaled clock has a frequency of f Table 11-4 on page 83 11.3.1.1 Prescaler Reset The prescaler is free running, i.e. it operates independently of the Clock Select logic ...
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... Signal description (internal signals): count clk top The counter is incremented at each timer clock (clk restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit located in the Timer/Counter Control Register (TCCR0A). For more details about counting sequences, see ATtiny261A/461A/861A Synchronization < ...
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Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk counter clear or ...
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... OCR0B), and whenever the Timer/Counter equals to the Output Compare Regisers, the comparator signals a match. A match will set the Output Compare Flag at the next timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag OCF0A or ATtiny261A/461A/861A 74 (Figure 11-4 on page 83). The edge detector is also 8197B– ...
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OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output ...
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... However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. ATtiny261A/461A/861A 76 Table 11-3 on page Figure ...
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Input Capture Mode The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see 75 for bit settings. For full description, see the section 11.7.5 16-bit Input Capture Mode The Timer/Counter0 can also be used in ...
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... Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be accessed with the temporary register 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATtiny261A/461A/861A 78 OCRnx - 1 OCRnx shows the setting of OCF0A and the clearing of TCNT0 in CTC mode ...
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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers. Assembly Code Example C Code Example unsigned int ...
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... SREG,r18 ret C Code Example unsigned int TIM0_ReadTCNT0( void ) { } Note: The assembly code example returns the TCNT0H/L value in the r17:r16 register pair. ATtiny261A/461A/861A 80 unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT0 into TCNT0L ...
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The following code examples show how atomic write of the TCNT0H/L register con- tents. Writing any of the OCR0A/B registers can be done by using the same principle. Assembly Code Example TIM0_WriteTCNT0: C Code Example void TIM0_WriteTCNT0( ...
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... These bits are reserved and will always read zero. • Bit 0 – CTC0: Waveform Generation Mode This bit controls the counting sequence of the counter, the source for maximum (TOP) counter value, see Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ation” on page ATtiny261A/461A/861A ...
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TCCR0B – Timer/Counter0 Control Register B Bit 0x33 (0x53) Read/Write Initial Value • Bit 4 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written ...
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... Bit 0x39 (0x59) Read/Write Initial Value • Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed ATtiny261A/461A/861A TCNT0H[7:0] ...
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Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is ...
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... TOP value, the ICF0 flag is set when the counter reaches the TOP value. ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by writing a logic one to its bit location. ATtiny261A/461A/861A 86 8197B–AVR–01/10 ...
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Timer/Counter1 12.1 Features • 8/10-Bit Accuracy • Three Independent Output Compare Units • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase and Frequency Correct Pulse Width Modulator (PWM) • Variable PWM Period • High Speed Asynchronous ...
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... The registers TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read ATtiny261A/461A/861A 88 “Pinout ATtiny261A/461A/861A” on page “Accessing 10-Bit Registers” on page shows Timer/Counter 1 synchronization register block diagram and describes syn- 2. The “ ...
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The read back values are delayed for the Timer/Counter1 (TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B, OCF1D and TOV1), because of the input and output synchronization. The system clock frequency ...
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... Control Register B” on page The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the sup- ply voltage below 2.7 volts are used. ATtiny261A/461A/861A 90 Definitions Description ...
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Prescaler Reset Setting the PSR1 bit in TCCR1B register resets the prescaler possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 12.3.1.2 Prescaler Initialization for Asynchronous Mode To change Timer/Counter1 to the asynchronous ...
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... For the normal mode of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym- ATtiny261A/461A/861A 92 Figure 12-5 shows a block diagram of the Output Compare unit. ...
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PWM pulses, thereby making the output glitch-free. See During the time between the write and the update operation, a read from OCR1A, OCR1B, OCR1C or OCR1D will read the contents of the temporary location. This means that the most ...
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... DT1H or DT1L value from DT1 I/O register, depending on the edge of the Waveform Output (OCW1x) when the dead time insertion is started. The Output Compare Output are delayed by one timer clock cycle at minimum from the Waveform Output when the Dead Time is adjusted to ATtiny261A/461A/861A 94 Figure 12-7 below ...
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The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit PWM1X is set. This will also cause both outputs to be high during the dead time. The length of the counting period is user adjustable by ...
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... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x and OC1x pins (DDR_OC1x and DDR_OC1x) must be set as output before the OC1x and OC1x values are visible on the pin. The port override function is independent of the Output Compare mode. ATtiny261A/461A/861A 96 WGM11 OC1OE1:0 ...
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The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. For Output Compare Pin Configurations refer to ...
Page 98
... Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the Phase and Frequency Correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and ATtiny261A/461A/861A 98 /4 when OCR1C is set to zero. The waveform frequency is defined by the following ...
Page 99
DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. The timing diagram for the fast PWM mode is shown in mented until the counter value matches the TOP value. The counter ...
Page 100
... The TCNT1 value will be equal to TOP for one timer clock cycle. The diagram includes the Waveform Output (OCW1x) in non-inverted and inverted Compare Output Mode. The small horizontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1. ATtiny261A/461A/861A 100 Table 12-3. ...
Page 101
Figure 12-13. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCWnx (COMnx = 2) OCWnx (COMnx = 3) Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to ...
Page 102
... TOP value. The counter is then cleared at the following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The tim- ing diagram includes Output Compare pins OC1A and OC1A, and the corresponding Output Compare Override Enable bits (OC1OE1:OC1OE0). ATtiny261A/461A/861A 102 Table 12-4. ...
Page 103
Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram TCNT1 OCW1A OC1OE0 OC1A Pin OC1OE1 OC1A Pin OC1OE2 OC1B Pin OC1OE3 OC1B Pin OC1OE4 OC1D Pin OC1OE5 OC1D Pin The general I/O port function is overridden by the Output Compare value ...
Page 104
... Phase and Frequency Correct PWM Mode. Figure 12-16. Timer/Counter Timing Diagram, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn TOVn Figure 12-17 ATtiny261A/461A/861A 104 Configuration of Output Compare Pins OC1D and OC1D in PWM6 Mode COM1D0 OC1D Pin (PB4) 0 Disconnected OC1OE4 1 OC1A • OC1OE4 0 OC1A • ...
Page 105
Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn OCRnx OCFnx Figure 12-18 Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn TOVn ...
Page 106
... If writing to more than one 10-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATtiny261A/461A/861A 106 Figure 11-3 on page 72). The edge 8197B– ...
Page 107
Code Examples The following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the TC1H register. The same principle can be used directly for accessing the OCR1A/B/C/D registers. Assembly Code Example C Code ...
Page 108
... SREG,r18 ret C Code Example unsigned int TIM1_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny261A/461A/861A 108 unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1 ...
Page 109
The following code examples show how atomic write of the TCNT1 register contents. Writing any of the OCR1A/B/C/D registers can be done by using the same principle. Assembly Code Example TIM1_WriteTCNT1: C Code Example void TIM1_WriteTCNT1( unsigned ...
Page 110
... The function of the COM1A1:0 bits depends on the PWM1A, WGM10 and WGM11 bit settings. Table 12-8 (non-PWM). Table 12-8. COM1A1 Table 12-9 are set to fast PWM mode. Table 12-9. COM1A1 ATtiny261A/461A/861A 110 COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R/W R ...
Page 111
Table 12-10 are set to Phase and Frequency Correct PWM Mode. Table 12-10. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1A1 Table 12-11 are set to single-slope PWM6 Mode. In the PWM6 Mode the ...
Page 112
... COM1B1 Bits COM1B1 and COM1B0 are shadowed in TCCR1C. Writing to bits COM1B1 and COM1B0 will also change bits COM1B1S and COM1B0S in TCCR1C. Similary, changes written to bits ATtiny261A/461A/861A 112 OCW1B Behaviour Normal port operation. Toggle on Compare Match. Clear on Compare Match. Set on Compare Match. ...
Page 113
COM1B1S and COM1B0S in TCCR1C will show here. See Register C” on page • Bit 3 - FOC1A: Force Output Compare Match 1A The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode. Writing a logical ...
Page 114
... Bits CS13, CS12, CS11, CS10: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source of Timer/Counter1. Table 12-17. Timer/Counter1 Prescaler Select CS13 The Stop condition provides a Timer Enable/Disable function. ATtiny261A/461A/861A 114 Table 12-16. DTPS10 Prescaler divides the T/C1 clock (no division CS12 CS11 CS10 Asynchronous Clocking Mode ...
Page 115
TCCR1C – Timer/Counter1 Control Register C Bit 0x27 (0x47) Read/Write Initial value • Bits 7,6 - COM1A1S, COM1A0S: Comparator A Output Mode, Shadow Bits 1 and 0 These are shadow bits of COM1A1 and COM1A0 in TCCR1A. Writing to ...
Page 116
... This bit selects which edge on the Fault Protection pin (INT0) is used to trigger a fault event. When the FPES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the FPES1 bit is written to one, a rising (positive) edge will trigger the fault. ATtiny261A/461A/861A 116 shows the COM1D1:0 bit functionality when the PWM1D and WGM11:10 bits are OCW1D Behaviour Normal port operation ...
Page 117
Bit 3 - FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to ...
Page 118
... PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 µs. After PLL lock- recommended to check the PLOCK bit before enabling PCK for Timer/Counter1. ATtiny261A/461A/861A 118 Output Compare Output ...
Page 119
TCNT1 – Timer/Counter1 Bit 0x2E (0x4E) Read/Write Initial value This 8-bit register contains the value of Timer/Counter1. The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data ...
Page 120
... Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and OCR1D to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow- ing the compare event. ATtiny261A/461A/861A 120 7 6 ...
Page 121
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section 12.12.13 TIMSK – Timer/Counter1 Interrupt Mask Register Bit ...
Page 122
... Bits 3:0- DT1L3:DT1L0: Dead Time Value for OC1x Output The dead time value for the OC1x output. The dead time delay is set as a number of the pres- caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. ATtiny261A/461A/861A 122 7 6 ...
Page 123
... A transparent latch between the output of the data register and the output pin delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin, regardless of the configuration. 8197B–AVR–01/10 “Pinout ATtiny261A/461A/861A” on page “Register Descriptions” on page 3 2 ...
Page 124
... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. ATtiny261A/461A/861A 124 Bit7 Bit6 ...
Page 125
Figure 13-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI The Three-wire mode timing is shown in Figure 13-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Data ...
Page 126
... The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed ( SCK CK SPITransfer_Fast: ret ATtiny261A/461A/861A 126 sbrs r16, USIOIF rjmp SPITransfer_loop lds r16,USIDR ret ...
Page 127
SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
Page 128
... In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and resetting the counter. ATtiny261A/461A/861A 128 Bit7 Bit6 ...
Page 129
The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight ...
Page 130
... The output will be changed immediately when a new MSB is written as long as the latch is open. Note that the Data Direction Register bit corresponding to the output pin must be set to one in order to enable data output from the USI Data Register. ATtiny261A/461A/861A 130 7 6 ...
Page 131
USIBR – USI Buffer Register Bit 0x10 (0x30) Read/Write Initial Value The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com- pleted, and instead of accessing the USI Data Register (the ...
Page 132
... Basically, only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. Table 13-1. USIWM1 0 0 ATtiny261A/461A/861A 132 USISIE USIOIE ...
Page 133
Table 13-1. USIWM1 1 1 Note: • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the USI Data Registerr and counter. The data output latch ensures that the output is changed at the opposite ...
Page 134
... Setting this bit to one changes the USI pin position. As default pins PB2:PB0 are used for the USI pin functions, but when writing this bit to one the USIPOS bit is set the USI pin functions are on pins PA2:PA0. ATtiny261A/461A/861A 134 Relations between the USICS1:0 and USICLK Setting (Continued) ...
Page 135
AC – Analog Comparator The analog comparator compares the input values on the selectable positive pin (AIN0, AIN1 or AIN2) and selectable negative pin (AIN0, AIN1 or AIN2). When the voltage on the positive pin is higher than the ...
Page 136
... Table 14-1. ACME ATtiny261A/461A/861A 136 Analog Comparator Multiplexed Input (Continued) ADEN MUX5:0 ACM2:0 x xxxxxx 100 x xxxxxx 101,110,111 1 xxxxxx 000 0 000000 000 0 000000 01x 0 000000 1xx 0 000001 000 0 000001 01x 0 000001 1xx 0 000010 000 0 000010 01x 0 000010 1xx 0 000011 000 0 000011 01x ...
Page 137
Register Description 14.2.1 ACSRA – Analog Comparator Control and Status Register A Bit 0x08 (0x28) Read/Write Initial Value • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the analog comparator ...
Page 138
... Bit 3 – AREFD: AREF Digital Input Disable When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre- sponding PIN register bit will always read as zero when this bit is set. When an analog signal is ATtiny261A/461A/861A 138 Table 14-2 ...
Page 139
AREF pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 14.2.4 DIDR1 – Digital Input Disable Register 1 Bit ...
Page 140
... Alternatively, V single ended channels. There is also an option to use an external voltage reference and turn-off the internal voltage reference. These options are selected using the REFS2:0 bits of the ADC- SRB and ADMUX registers. ATtiny261A/461A/861A 140 ADC Input Voltage Range 141. ...
Page 141
Figure 15-1. Analog to Digital Converter Block Schematic 8-BIT DATA BUS VCC AREF INTERNAL 2.56/1.1V INTERNAL 1.18V AGND ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 15.3 Operation The ADC converts an analog input voltage to a ...
Page 142
... When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting con- versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new ATtiny261A/461A/861A 142 Table ...
Page 143
If another positive edge occurs on the trigger signal during con- version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global ...
Page 144
... In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. Figure 15-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATtiny261A/461A/861A 144 Figure 15-3. Figure 15-4 below. First Conversion 1 2 ...
Page 145
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See 15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock ...
Page 146
... In Free Running mode, always select the channel before starting the first conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel ATtiny261A/461A/861A 146 Table 15-1 ...
Page 147
Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 15.6.2 ADC Voltage Reference The conversion range of the ADC is defined by the ...
Page 148
... ADC Noise Reduction Mode 15.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior: ATtiny261A/461A/861A 148 I IH ADCn ...
Page 149
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 15-9. Offset Error Output Code • Gain Error: After adjusting for offset, the Gain Error is ...
Page 150
... Figure 15-11. Integral Non-linearity (INL) Output Code • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 15-12. Differential Non-linearity (DNL) ATtiny261A/461A/861A 150 Output Code 0x3FF 1 LSB ...
Page 151
Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum ...
Page 152
... ADCH and ADCL are the ADC data registers the fixed slope coefficient and T the temperature sensor offset. Typically very close to 1.0 and in single-point calibration the coefficient may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measurements at two temperatures. ATtiny261A/461A/861A 152 ( V ...
Page 153
Register Description 15.13.1 ADCSRA – ADC Control and Status Register A Bit 0x06 (0x26) Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC ...
Page 154
... If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in page 151. 15.13.3 ADMUX – ADC Multiplexer Selection Register Bit 0x07 (0x27) Read/Write Initial Value ATtiny261A/461A/861A 154 ADC Prescaler Selections (Continued) ADPS1 ...
Page 155
Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits These bits together with the REFS2 bit from the ADC Control and Status Register B (ADCSRB) select the voltage reference for the ADC, as shown in Table 15-4. REFS2 X X ...
Page 156
... ATtiny261A/461A/861A 156 Table 15-5 for details. Input Channel Selections Single-Ended Input Positive ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA4) ADC4 (PA5) ADC5 (PA6) NA ADC6 (PA7) ...
Page 157
Table 15-5. MUX5:0 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Note: 8197B–AVR–01/10 Input Channel Selections ...
Page 158
... ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the ATtiny261A/461A/861A 158 7 ...
Page 159
If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set Table 15-6. ADTS2 15.13.5 DIDR0 – Digital ...
Page 160
... The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. Figure 16-1. The debugWIRE Setup When designing a system where debugWIRE will be used, the following must be observed: ATtiny261A/461A/861A 160 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator dW ...
Page 161
Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to V • Capacitors inserted on the RESET pin must be ...
Page 162
... Page Write operation or by writing the CTPB bit in SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. ATtiny261A/461A/861A 162 The CPU is halted during the Page Erase operation. ...
Page 163
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 17.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR ...
Page 164
... Read the FLB from the LPM destination register. If successful, the contents of the destination register are as follows. Bit Rd Refer to ATtiny261A/461A/861A 164 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro- grammed, will be read as one. 7 ...
Page 165
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd Refer to To read the Fuse ...
Page 166
... SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. ATtiny261A/461A/861A 166 7 6 ...
Page 167
... Memory Programming This section describes the different methods for programming ATtiny261A/461A/861A memories. 18.1 Program And Data Memory Lock Bits The device provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in with the Chip Erase command. ...
Page 168
... Note that the fuses are read as logical zero, “0”, if they are programmed. Table 18-3. Fuse High Byte SELFPRGEN Notes: Table 18-4. Fuse High Byte RSTDISBL DWEN SPIEN WDTON EESAVE BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes: ATtiny261A/461A/861A 168 Table 18-3, Fuse Extended Byte Bit No Description ...
Page 169
... High-voltage Programming mode, also when the device is locked. The three bytes reside in a separate address space. The signature bytes are given in Table 18-6. Table 18-6. Parts ATtiny261A ATtiny461A ATtiny861A 18.4 Calibration Byte The signature area has one byte of calibration data for the internal oscillator. This byte resides in the high byte of address 0x000 ...
Page 170
... Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See Figure 18-1. Serial Programming and Verify Note: ATtiny261A/461A/861A 170 No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size ...
Page 171
After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Table 18-9. Note: When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial ...
Page 172
... Programming Enable Chip Erase (Program Memory/EEPROM) Poll RDY/BSY Load Instructions (1) Load Extended Address byte Load Program Memory Page, High byte ATtiny261A/461A/861A 172 before issuing the next byte. (See WD_EEPROM Table 18-8 chip erased device, no 0xFF in the data file(s) need to power off. ...
Page 173
... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘ ...
Page 174
... Data memory, Memory Lock bits, and Fuse bits. Pulses are assumed least 250 ns in length, unless otherwise noted. 18.7.1 Signal Names In this section, some pins are referenced by signal names describing their functionality during parallel programming, see are referenced by pin names. ATtiny261A/461A/861A 174 Serial Programming Instruction Byte 1 Byte 4 Adr LSB 0 ...
Page 175
Figure 18-3. Parallel Programming. Table 18-12. Pin Name Mapping Signal Name in Programming Mode XA1/BS2 PAGEL/BS1 RDY/BSY DATA I/O 8197B–AVR–01/10 WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 XTAL1/PB4 OE PB5 RDY/BSY PB6 +12 V RESET GND Pin Name I/O ...
Page 176
... The bit coding is shown in Table 18-14. XA1 and XA0 Coding XA1 When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 18-15. Command Byte Bit Coding Command Byte ATtiny261A/461A/861A 176 Pin PAGEL/BS1 Prog_enable[3] XA1/BS2 Prog_enable[2] XA0 Prog_enable[1] WR Prog_enable[0] Table 18-14 ...
Page 177
Entering Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between V 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set Prog_enable pins listed in ns. ...
Page 178
... While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. ATtiny261A/461A/861A 178 RDY/BSY goes low. nals are reset. ...
Page 179
Figure 18-4. Addressing the Flash Which is Organized in Pages PROGRAM MEMORY Note: In the figure below, “XX” means don’t care. The numbers in the figure refer to the programming description above. WR Figure 18-5. Flash Programming Waveforms STEP DATA ...
Page 180
... Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA. 5. Set BS to “1”. The Flash word high byte can now be read at DATA. 6. Set OE to “1”. ATtiny261A/461A/861A 180 “Programming the Flash” on page 177 RDY/BSY goes low ...
Page 181
Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to on page 177 1. A: Load Command “0000 0011” Load Address High Byte (0x00 - 0xFF Load Address Low Byte ...
Page 182
... Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed). 5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed). 6. Set OE to “1”. ATtiny261A/461A/861A 182 Write Fuse Low byte A C ...
Page 183
Figure 18-8. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte Extended Fuse Byte Fuse High Byte 18.7.14 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ...
Page 184
... Input Leakage I IL Current I/O Pin Input Leakage I IH Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor PU ATtiny261A/461A/861A 184 *NOTICE: +0. -40°C to 85° 1.8V to 5.5V (unless otherwise noted Condition Min Except XTAL1 and -0.5 RESET pins XTAL1 pin, -0 ...
Page 185
Table 19-1. DC Characteristics. T Symbol Parameter Power Supply Current I CC Power-down mode Notes: 1. “Min” means the lowest value where the pin is guaranteed to be read as high. 2. “Max” means the highest value where the pin ...
Page 186
... CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL Δ t Change in period from one clock cycle to the next CLCL ATtiny261A/461A/861A 186 Figure 20-49 on page 219 V Temperature CC 3V 25°C Fixed temperature Fixed voltage within: within: 1.8V - 5.5V -40°C - 85° 1 ...
Page 187
System and Reset Characteristics Table 19-4. Symbol V RST t RST V HYST t BOD Notes: 19.5.1 Enhanced Power-On Reset Table 19-5. Symbol V POR V POA SR ON Note: 19.5.2 Brown-Out Detection ...
Page 188
... Internal 1.1V Reference V INT Internal 2.56V Reference R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output Note must be below V . DIFF REF 2. Not tested in production. ATtiny261A/461A/861A 188 Condition 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 1 MHz 4V, ...
Page 189
Serial Programming Characteristics Figure 19-3. Serial Programming Waveforms SERIAL DATA INPUT SERIAL DATA OUTPUT SERIAL CLOCK INPUT Figure 19-4. Serial Programming Timing Table 19-8. Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH ...
Page 190
... XA0, XA1/BS2, PAGEL/BS1) WR RDY/BSY Figure 19-6. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in ATtiny261A/461A/861A 190 t XLWL t XHXL t t DVXH XLDX t t BVPH PLBX ...
Page 191
Figure 19-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS (LOW BYTE) XTAL1 PAGEL/BS1 OE DATA ADDR0 (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in Table 19-9. Symbol ...
Page 192
... Table 19-9. Symbol t BVDV t OLDV t OHDZ Notes: ATtiny261A/461A/861A 192 Parallel Programming Characteristics, V Parameter BS1 Valid to DATA valid OE Low to DATA Valid OE High to DATA Tri-stated valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits WLRH commands valid for the Chip Erase command. ...
Page 193
Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
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... TIMER0, 27.3 % for the ADC, and 6.5 % for the USI module. Reading from on page The total current consumption in idle mode with TIMER0, ADC, and USI enabled, gives: ≈ total ATtiny261A/461A/861A 194 Additional Current Consumption (percentage) in Active and Idle mode. Additional Current consumption compared to Active with external clock (see Figure 20-1 on page ...
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... ATtiny261A 20.2.1 Current Consumption in Active Mode Figure 20-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.8 0.6 0.4 0.2 Figure 20-2. Active Supply Current vs. Frequency ( MHz) 8197B–AVR–01/10 ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 0.2 0.3 0.4 Frequency (MHz) ACTIVE SUPPLY CURRENT vs ...
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... Figure 20-3. Active Supply Current vs. V Figure 20-4. Active Supply Current vs. V ATtiny261A/461A/861A 196 CC ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE 1 ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, 1 MHz 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 (Internal Calibrated Oscillator, 8 MHz) INTERNAL OSCILLATOR, 8 MHz 3 ...
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Figure 20-5. Active Supply Current vs. V 20.2.2 Current Consumption in Idle Mode Figure 20-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 8197B–AVR–01/10 ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 ...
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... Figure 20-7. Idle Supply Current vs. Frequency ( MHz) Figure 20-8. Idle Supply Current vs. V ATtiny261A/461A/861A 198 IDLE SUPPLY CURRENT vs. FREQUENCY 3 2.5 2 1.5 1 0.5 1 Frequency (MHz) (Internal Calibrated Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL OSCILLATOR, 8 MHz 1.4 1.2 1 0.8 0.6 0.4 0 ...
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Figure 20-9. Idle Supply Current vs. V Figure 20-10. Idle Supply Current vs. V 0.025 0.02 0.015 0.01 0.005 8197B–AVR–01/10 CC IDLE SUPPLY CURRENT vs. V INTERNAL OSCILLATOR, 1 MHz 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 ...
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... Current Consumption in Power-Down Mode Figure 20-11. Power-down Supply Current vs. V Figure 20-12. Power-down Supply Current vs. V ATtiny261A/461A/861A 200 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.5 2 2.5 3 (Watchdog Timer Disabled) ...