PIC16F688-E/ST Microchip Technology, PIC16F688-E/ST Datasheet - Page 66
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PIC16F688-E/ST
Manufacturer Part Number
PIC16F688-E/ST
Description
IC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-EP.pdf
(174 pages)
Specifications of PIC16F688-E/ST
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
14-TSSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
256 B
Height
0.9 mm
Length
5 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
4.4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC16F688
8.1.4
The A/D conversion cycle requires 11 T
of the conversion clock is software selectable via the
ADCS bits (ADCON1<6:4>). There are seven possible
clock options:
• F
• F
• F
• F
• F
• F
• F
TABLE 8-1:
8.1.5
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 T
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
DS41203B-page 64
Legend: Shaded cells are outside of recommended range.
Note 1:
Note:
Operation
AD
OSC
OSC
OSC
OSC
OSC
OSC
RC
16 T
32 T
64 T
A/D RC
2 T
4 T
8 T
A/D Clock Source (T
delay is required before another acquisition can
(dedicated internal oscillator)
2:
3:
4:
/2
/4
/8
/16
/32
/64
OSC
OSC
OSC
OSC
OSC
OSC
conversion
The A/D RC source has a typical T
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
CONVERSION CLOCK
STARTING A CONVERSION
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
T
AD
ADCS<2:0>
vs. DEVICE OPERATING FREQUENCIES
000
100
001
101
010
110
x11
sample.
AD
)
Instead,
AD
2-6 s
. The source
100 ns
200 ns
400 ns
800 ns
20 MHz
1.6 s
3.2 s
AD
(1,4)
(2)
(2)
(2)
(2)
time of 4 s for V
Preliminary
the
AD
time.
2-6 s
12.8 s
400 ns
800 ns
For correct conversion, the A/D conversion clock
(1/T
1.6 s. Table 8-1 shows a few T
selected frequencies.
5 MHz
1.6 s
3.2 s
6.4 s
DD
AD
Device Frequency
(1,4)
(2)
(2)
(3)
) must be selected to ensure a minimum T
> 3.0V.
2-6 s
16.0 s
500 ns
1.0 s
8.0 s
4 MHz
2.0 s
4.0 s
2004 Microchip Technology Inc.
(1,4)
(2)
(3)
(2)
(3)
AD
calculations for
2-6 s
1.25 MHz
12.8 s
25.6 s
51.2 s
1.6 s
3.2 s
6.4 s
(1,4)
(3)
(3)
(3)
AD
of