AT89LP216-20SU Atmel, AT89LP216-20SU Datasheet - Page 36
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AT89LP216-20SU
Manufacturer Part Number
AT89LP216-20SU
Description
MCU 8051 2K FLASH 20MHZ 16-SOIC
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP216-20PU.pdf
(98 pages)
Specifications of AT89LP216-20SU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
14
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
15. External Interrupts
16. General-purpose Interrupts
.
Table 16-1.
36
GPMOD = 9AH
Not Bit Addressable
Bit
AT89LP216
GPMOD.x
GPMOD7
GPMOD
7
– General-purpose Interrupt Mode Register
When the AT89LP216 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be
used as the INT0 and INT1 external interrupt sources. When the external clock source is used,
XTAL2 is available as INT1. Neither interrupt is available in crystal oscillator mode.The external
interrupts can be programmed to be level-activated or transition-activated by setting or clearing
bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at
the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples
of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in
TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sam-
pled once each clock cycle, an input high or low should hold for at least 2 oscillator periods to
ensure sampling. If the external interrupt is transition-activated, the external source has to hold
the request pin high for at least two clock cycles, and then hold it low for at least two clock cycles
to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be auto-
matically cleared by the CPU when the service routine is called if generated in edge-triggered
mode. If the external interrupt is level-activated, the external source has to hold the request
active until the requested interrupt is actually generated. Then the external source must deacti-
vate the request before the interrupt service routine is completed, or else another interrupt will
be generated.
The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on
Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register
select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS regis-
ters determine the mode for each individual pin. GPMOD selects between level-sensitive and
edge-triggered mode. GPLS selects between high/low in level mode and positive/negative in
edge mode. The pins of Port 1 are sampled every clock cycle. In level-sensitive mode, a valid
level must appear in two successive samples before generating the interrupt. In edge-triggered
mode, a transition will be detected if the value changes from one sample to the next. When an
interrupt condition on a pin is detected, and that pin is enabled, the appropriate flag in the GPIF
register is set. The flags in GPIF must be cleared by software.
0 = level-sensitive interrupt for P1.x
1 = edge-triggered interrupt for P1.x
GPMOD6
6
GPMOD5
5
GPMOD4
4
GPMOD3
3
GPMOD2
2
Reset Value = 0000 0000B
GPMOD1
1
GPMOD0
3621E–MICRO–11/10
0