ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet - Page 216

• Manufacturer Part Number: ATTINY48-MMU
• Description: MCU AVR 5K FLASH 12MHZ 28-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, I2S, SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28VQFN EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 22-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
Note:
216
DATA
CLKI
BS1
XA0
XA1
OE
1. The timing requirements shown in
ATtiny48/88
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
Table 22-9.
Symbol
V
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
PP
t
XLOL
t
OLDV
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before CLKI High
CLKI Low to CLKI High
CLKI Pulse Width High
Data and Control Hold after CLKI Low
CLKI Low to WR Low
CLKI Low to PAGEL high
PAGEL low to CLKI high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
Parallel Programming Characteristics, T
Figure 22-6
DATA (Low Byte)
READ DATA
(LOW BYTE)
(i.e., t
DVXH
, t
XHXL
t
BVDV
, and t
XLDX
(HIGH BYTE)
READ DATA
DATA (High Byte)
) also apply to reading operation.
A
= 25°C, V
11.5
Min
200
150
150
150
150
67
67
67
67
67
67
67
0
0
0
t
OHDZ
CC
= 5V
Typ
LOAD ADDRESS
(LOW BYTE)
ADDR1 (Low Byte)
Max
12.5
250
1
8008G–AVR–04/11
Units
(1)
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
V