PIC16F627A-E/SO Microchip Technology, PIC16F627A-E/SO Datasheet - Page 80
![IC MCU FLASH 1KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F627A-E/SO
Manufacturer Part Number
PIC16F627A-E/SO
Description
IC MCU FLASH 1KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
5.PIC16F627A-ISO.pdf
(168 pages)
Specifications of PIC16F627A-E/SO
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIP
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F627A-IP PDF datasheet #2
- PIC16F627A-IP PDF datasheet #3
- PIC16F627A-IP PDF datasheet #4
- PIC16F627A-ISO PDF datasheet #5
- Current page: 80 of 168
- Download datasheet (3Mb)
PIC16F627A/628A/648A
FIGURE 12-7:
TABLE 12-6:
DS40044B-page 78
Legend: x = unknown, - = unimplemented locations read as ‘0’.
Address
0Ch
8Ch
18h
19h
98h
99h
TXIF bit
(interrupt reg. flag)
RB2/TX/CK (pin)
TRMT bit
(Transmit shift
reg. empty flag)
Write to TXREG
BRG output
(shift clock)
Shaded cells are not used for Asynchronous Transmission.
Note:
TXREG USART Transmit data register
SPBRG Baud Rate Generator Register
RCSTA
TXSTA
Name
PIR1
PIE1
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
This timing diagram shows two consecutive transmissions.
.
CSRC
SPEN
EEIF
EEIE
Bit 7
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Transmit Shift Reg.
WORD 1
Word 1
CMIF
CMIE
Bit 6
RX9
TX9
Start Bit
Word 2
SREN
TXEN
RCIF
RCIE
Bit 5
CREN
SYNC
Bit 4
TXIF
TXIE
Bit 0
Preliminary
ADEN
Bit 3
—
—
—
Bit 1
WORD 1
CCP1IF
CCP1IE TMR2IE
BRGH
FERR
Bit 2
TMR2IF
OERR
TRMT
Bit 1
Bit 7/8
WORD 2
Transmit Shift Reg.
TMR1IE
TMR1IF
RX9D
TX9D
Bit 0
2004 Microchip Technology Inc.
Stop Bit
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
Value on
POR
Start Bit
WORD 2
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
Value on
all other
Resets
Bit 0
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