ATTINY88-MMU Atmel, ATTINY88-MMU Datasheet - Page 201
ATTINY88-MMU
Manufacturer Part Number
ATTINY88-MMU
Description
MCU AVR 8K FLASH 12MHZ 28-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-MMU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
ATTINY88-MMU
Manufacturer:
ATMEL
Quantity:
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Part Number:
ATTINY88-MMU
Manufacturer:
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8008G–AVR–04/11
Figure 21-7. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction.
The Chip Erase operation turns the content of every memory location in both the Program and
EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
• Minimum low period of serial clock:
• Minimum high period of serial clock:
– When f
– When f
– When f
– When f
1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the
2. V
CLKI pin.
CC
ck
ck
ck
ck
- 0.3V <
< 12MHz: > 2 CPU clock cycles
>= 12MHz: 3 CPU clock cycles
< 12MHz: > 2 CPU clock cycles
>= 12MHz: 3 CPU clock cycles
MOSI
MISO
SCK
AV
CC
< V
CC
+ 0.3V, however, AV
CLKI
RESET
GND
(1)
CC
should always be within 1.8 – 5.5V
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
ATtiny48/88
(2)
201
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