ATMEGA48P-20MMUR Atmel, ATMEGA48P-20MMUR Datasheet - Page 175
![MCU AVR 4K FLASH 20MHZ 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA48P-20MMUR
Manufacturer Part Number
ATMEGA48P-20MMUR
Description
MCU AVR 4K FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA168P-20AU.pdf
(420 pages)
Specifications of ATMEGA48P-20MMUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.3
8025L–AVR–7/10
Clock Generation
Figure 19-1. USART Block Diagram
Note:
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
1. Refer to
Figure 1-1 on page 2
UCSRnA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn(Transmit)
UBRRn [H:L]
(1)
and
Table 13-9 on page 86
UCSRnB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
ATmega48P/88P/168P
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
for USART0 pin placement.
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRnC
XCKn
TxDn
RxDn
175
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