PIC12CE519-04/P Microchip Technology, PIC12CE519-04/P Datasheet - Page 665

• Manufacturer Part Number: PIC12CE519-04/P
• Description: IC MCU OTP 1KX12 W/EE 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE519-04/P

• Program Memory Type: OTP
• Program Memory Size: 1.5KB (1K x 12)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Eeprom Size: 16 x 8
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

APPENDIX C: DEVICE ENHANCEMENT
C.1
1997 Microchip Technology Inc.
Data Memory Map
As the Midrange architecture matured, certain modules and features have been enhanced. They
are:
1.
2.
3.
4.
5.
6.
7.
The following subsections discuss the implementations of these enhancements.
The Data Memory Map shows the location of the Special Function Registers (SFRs) and the
General Purpose Registers (GPRs). SFRs provide controls and give status on the operation of
the device, while the GPRs are the general purpose RAM.
Figure C-1
Memory Map A was implemented on the first midrange devices. They were 18/20-pin devices
that had limited peripheral features. When the product roadmap dictated the requirement for
devices with increased I/O, and a richer peripheral set, memory map B was implemented. Mem-
ory map C is actually a subset of memory map B, but context saving (due to an interrupt) requires
additional software overhead. This is because there is no GPR in Bank1. To minimize the context
saving software, memory map D was defined. A common RAM memory map will be used for all
future devices. See the
Midrange PICmicro’s memory.
Figure C-1:
A
The data memory map
The SSP module
The A/D module
Brown-out Reset added to the core
MCLR Filter
USART
Device Oscillator
0Ch
Note 1: Mapped in Bank0.
0Bh
00h
7Fh
1Fh
7Fh
00h
20h
70h
Bank0 Bank1
GPR
2: Unimplemented, read as '0'.
3: Some devices have some GPR located in the SFR region.
SFR
show the various memory maps that have been implemented in the midrange family.
D
Bank0
SFR
GPR
(3)
SFR
Various Data Memory Maps
(1)
80h
9Fh
A0h
F0h
FFh
80h
8Bh
8Ch
FFh
“Memory Organization”
Bank1
GPR
SFR
(1)
1Fh
7Fh
00h
20h
170h
17Fh
100h
11Fh
120h
B
Bank0 Bank1
GPR
SFR
Bank2
GPR
SFR
(1)
GPR
SFR
180h
19Fh
1A0h
1F0h
1FFh
section for use and implementation of the
80h
9Fh
A0h
FFh
Bank3
GPR
SFR
(1)
1Fh
7Fh
Appendix C
00h
20h
Bank0 Bank1
C
GPR
SFR
DS31034A-page 34-13
SFR
(2)
80h
9Fh
A0h
FFh
34