PIC16F636-I/ML Microchip Technology, PIC16F636-I/ML Datasheet - Page 137
![IC PIC MCU FLASH 2KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F636-I/ML
Manufacturer Part Number
PIC16F636-I/ML
Description
IC PIC MCU FLASH 2KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F635-ISN.pdf
(234 pages)
3.PIC16F636-ISL.pdf
(8 pages)
4.PIC16F636-ISL.pdf
(4 pages)
Specifications of PIC16F636-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, WDT
Number Of I /o
11
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Controller Family/series
PIC16F
No. Of I/o's
12
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
2
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232, SPI, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162057 - MPLAB ICD 2 HEADER 14DIP
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F636-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
12.7
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
Configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit erased (PWRT disabled),
there will be no time-out at all. Figure 12-4, Figure 12-5
and Figure 12-6 depict time-out sequences. The device
can execute code from the INTOSC, while OST is active,
by enabling Two-Speed Start-up or Fail-Safe Clock
Monitor (See Section 3.7.2 “Two-Speed Start-up
Sequence”
Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to
PIC12F635/PIC16F636/639 device operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
TABLE 12-1:
TABLE 12-2:
TABLE 12-3:
© 2007 Microchip Technology Inc.
XT, HS, LP
RC, EC, INTOSC
CONFIG
PCON
STATUS
Legend:
Note
Legend: u = unchanged, x = unknown
Configuration
Name
POR
Oscillator
0
u
u
u
u
u
u
u
1:
2:
(2)
synchronize
Time-out Sequence
BOREN1 BOREN0
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 12-1) for operation of all register bits.
Bit 9
BOR
and
x
0
u
u
u
u
u
0
TIME-OUT IN VARIOUS SITUATIONS
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
PCON BITS AND THEIR SIGNIFICANCE
T
Section 3.8
PWRT
Bit 8
WUR
PWRTE = 0
x
u
u
u
u
u
0
u
more
+ 1024 • T
T
PWRT
Bit 7
CPD
IRP
—
Power-up
“Fail-Safe
TO
OSC
1
1
0
0
u
1
1
1
Bit 6
RP1
CP
—
than
ULPWUE SBOREN
PWRTE = 1
1024 • T
MCLRE
Bit 5
RP0
PD
Clock
1
1
u
0
u
0
0
1
PIC12F635/PIC16F636/639
—
one
OSC
PWRTE
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
Wake-up Reset during Sleep
Brown-out Reset during Sleep
Bit 4
TO
T
PWRT
12.8
The Power Control register, PCON (address 8Eh), has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 4.2.3 “Ultra
Low-Power Wake-up” and Section 12.6 “Brown-out
Reset (BOR)”.
WDTE
WUR
Bit 3
PD
PWRTE = 0
+ 1024 • T
T
PWRT
FOSC2
Brown-out Reset
Bit 2
Power Control (PCON) Register
—
Z
FOSC1
OSC
Bit 1
POR
DC
Condition
FOSC0
1024 • T
PWRTE = 1
Bit 0
BOR
C
—
--01 --qq
0001 1xxx
POR, BOR
OSC
Value on
—
DS41232D-page 135
DD
1024 • T
from Sleep
Wake-up
--0u --uu
000q quuu
may have
Resets
Value on
all other
—
—
OSC
(1)