PIC16F1826-I/ML Microchip Technology, PIC16F1826-I/ML Datasheet - Page 24
PIC16F1826-I/ML
Manufacturer Part Number
PIC16F1826-I/ML
Description
IC PIC MCU FLASH 2K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1826-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
3
Interface
EUSART, I2C, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 24 of 406
- Download datasheet (4Mb)
PIC16F/LF1826/27
3.2.2
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers asso-
ciated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
3.2.3
There are up to 80 bytes of GPR in each data memory
bank.
3.2.3.1
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-3:
DS41391C-page 24
7-bit Bank Offset
SPECIAL FUNCTION REGISTER
GENERAL PURPOSE RAM
COMMON RAM
Linear Access to GPR
0Bh
0Ch
1Fh
6Fh
7Fh
00h
20h
70h
Special Function Registers
BANKED MEMORY
PARTITIONING
General Purpose RAM
(20 bytes maximum)
(80 bytes maximum)
Memory Region
Core Registers
Common RAM
(12 bytes)
(16 bytes)
Preliminary
3.2.5
The memory maps for the device family are as shown
in Table 3-2.
TABLE 3-2:
PIC16F/LF1826/27
Device
DEVICE MEMORY MAPS
MEMORY MAP TABLES
2010 Microchip Technology Inc.
Banks
16-23
24-31
8-15
0-7
31
Table No.
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
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