PIC16LF1826-I/ML Microchip Technology, PIC16LF1826-I/ML Datasheet - Page 326
![IC MCU 8BIT FLASH 28QFN](/photos/18/99/189937/4243194_sml.jpg)
PIC16LF1826-I/ML
Manufacturer Part Number
PIC16LF1826-I/ML
Description
IC MCU 8BIT FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1826-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16LF
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
3
Interface
EUSART, I2C, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF1826/27
TABLE 28-3:
DS41391B-page 326
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
MOVWI
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
Mnemonic,
Operands
2:
is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
k
–
k
–
k
k
k
–
–
–
–
–
–
f
n, k
n mm
k[n]
n mm
k[n]
PIC16F/LF1826/27 ENHANCED INSTRUCTION SET (CONTINUED)
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
Add Literal to FSRn
Move INDFn to W, with pre/post inc/dec
Move INDFn to W, Indexed Indirect.
Move W to INDFn, with pre/post inc/dec
Move W to INDFn, Indexed Indirect.
Description
C-COMPILER OPTIMIZED
INHERENT OPERATIONS
CONTROL OPERATIONS
Preliminary
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
Cycles
11
00
10
00
10
00
11
00
00
00
00
00
00
00
MSb
11
00
11
00
11
14-Bit Opcode
001k
0000
0kkk
0000
1kkk
0000
0100
0000
0000
0000
0000
0000
0000
0000
0001
0000
1111
0000
1111
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
0110
0000
0110
0000
0110
0110
0nkk
1nkk
0nkk
0001
0001
© 2009 Microchip Technology Inc.
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
0100
0000
0010
0001
0011
0fff
0nmm
kkkk
kkkk
kkkk
1nmm
LSb
TO, PD
TO, PD
Z
Z
Affected
Status
2
2
2
2
Notes
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