AT90PWM2-16SQ Atmel, AT90PWM2-16SQ Datasheet
AT90PWM2-16SQ
Specifications of AT90PWM2-16SQ
Related parts for AT90PWM2-16SQ
AT90PWM2-16SQ Summary of contents
Page 1
... Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) ® ® AVR 8-bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B 4317J–AVR–08/10 ...
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... Register – PICR0H and PICR0L” on page 169. • Add bits to read the PSC output activity - Register – PIFR0” on page 171. • Add some clock configurations - AT90PWM2B/3B” on page 30. • Change Amplifier Synchonization - See “” on page 253. • Correction of the Errata - See “ ...
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... PD0 (INT3/PSCOUT10) PC0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 (PSCIN1/OC1B) PC1 VCC GND (T0/PSCOUT22) PC2 (T1/PSCOUT23) PC3 (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 AT90PWM2/3/2B/3B AT90PWM2/2B SOIC24 1 24 PB7(ADC4/PSCOUT01/SCK PB6 (ADC7/ICP1B) PB5 (ADC6/INT2 PB4 (AMP0 PB3 (AMP0-) ...
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... Figure 3-3. (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 3.1 Pin Descriptions : Table 3-1. Pin out description S024 Pin SO32 Pin QFN32 Pin Number Number Number AT90PWM2/3/2B/3B 4 QFN32 (7*7 mm) Package. AT90PWM3/3B QFN (PSCIN1/OC1B) PC1 3 VCC 4 GND 5 (T0/PSCOUT22) PC2 6 (T1/PSCOUT23) PC3 7 (MISO/PSCOUT20) PB0 8 Mnemonic Type ...
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... PC4 AMP1- (Analog Differential Amplifier 1 Input Channel ) ADC9 (Analog Input Channel 9) PC5 I/O AMP1+ (Analog Differential Amplifier 1 Input Channel ) ADC10 (Analog Input Channel 10) PC6 I/O ACMP1 (Analog Comparator 1 Positive Input ) PC7 I/O D2A : DAC output AT90PWM2/3/2B/3B Name, Function & Alternate Function 5 ...
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... Overview The AT90PWM2/2B/3/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. AT90PWM2/3/2B/3B 6 Mnemonic Type ...
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... CISC microcontrollers. The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex- ...
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... As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C is not available on 24 pins package. Port C also serves the functions of special features of the AT90PWM2/2B/3/3B as listed on 70. AT90PWM2/3/2B/ ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed on page 4 ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. AT90PWM2/3/2B/3B 10 Block Diagram of the AVR Architecture ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM2/2B/3/3B has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. AT90PWM2/3/2B/ ...
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... R17 … R26 R27 R28 R29 R30 R31 Figure 5-2, each register is also assigned a data memory address, mapping them The X-, Y-, and Z-registers 15 XH AT90PWM2/3/2B/3B Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... No internal clock division is used. Figure 5-4 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. AT90PWM2/3/2B/ R27 (0x1B) 15 ...
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... Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back for details. 264. AT90PWM2/3/2B/ “Interrupts” on page “Interrupts” on page 56 “Boot Loader Support – Read-While-Write Self-Pro “Memory Program- 56 ...
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... CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. AT90PWM2/3/2B/3B 16 Assembly Code Example in r16, SREG ...
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... Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ AT90PWM2/3/2B/3B 17 ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM2/2B/3/3B Program Counter (PC bits wide, thus addressing the 4K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in gramming” ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the AT90PWM2/2B/3/3B are all accessible through all these addressing modes. The Register File is described in page 13 ...
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... Figure 3. On-chip Data SRAM Access Cycles 6.3 EEPROM Data Memory The AT90PWM2/2B/3/3B contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space ...
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... When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. AT90PWM2/3/2B/3B 22 “Boot Loader for details about Boot ...
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... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 4317J–AVR–08/10 EEPROM Programming Time. Number of Calibrated RC Oscillator Cycles 26368 AT90PWM2/3/2B/3B Table 6-2 lists the typical pro- Typ Programming Time 3 ...
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... EEPROM_write (unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } AT90PWM2/3/2B/ 4317J–AVR–08/10 ...
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... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, AT90PWM2/3/2B/3B reset Protection circuit can CC 25 ...
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... The I/O space definition of the AT90PWM2/2B/3/3B is shown in 335. All AT90PWM2/2B/3/3B I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... General Purpose I/O Register 3– GPIOR3 Bit Read/Write Initial Value 4317J–AVR–08/ GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 R/W R/W R/W R AT90PWM2/3/2B/ GPIOR3 R/W R/W R/W R ...
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... Sleep Modes” on page Figure 7-1. AT90PWM2/3/2B/3B 28 presents the principal clock systems in the AVR and their distribution. All of the clocks 40. The clock systems are detailed below. Clock Distribution AT90PWM2/3 PSC0/1/2 General I/O ADC Modules CLK clk ...
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... CPU clock. 7.1.4 PLL Clock – clk PLL The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock MHz clock is also derived for the CPU. 4317J–AVR–08/10 Clock Distribution AT90PWM2B/3B PSC0/1/2 General I/O ADC Modules CLK clk ...
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... The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start- AT90PWM2/3/2B/3B 30 Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. Device Clocking Options Select AT90PWM2B/3B (1) AT90PWM2/3 CKSEL3..0 1111 - 1000 0111- 0100 ...
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... Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( Table 7-4. For ceramic resonators, the capacitor values given by Crystal Oscillator Connections C2 C1 AT90PWM2/3/2B/3B “Watchdog Oscillator = 3.0V) Number of Cycles CC 4 (4,096 64K (65,536) Figure 7-3. Either a quartz crystal or a XTAL2 XTAL1 ...
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... Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse programmed. See more details. AT90PWM2/3/2B/3B 32 Crystal Oscillator Operating Modes (1) Frequency Range ...
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... The device is shipped with this option selected. Oscillator Calibration Register – OSCCAL CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value AT90PWM2/3/2B/3B “Oscillator Calibration Register – OSCCAL” on Table 26-1 on page 282. (1)(2) CKSEL3..0 0010 Additional Delay from Reset (V = 5.0V) CC (1) 14CK 14CK + 4 ...
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... Internal PLL for PSC The internal PLL in AT90PWM2/2B/3/3B generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1 MHz. See the The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time ...
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... This value do not provide a proper restart ; do not use PD in this clock scheme This value do not provide a proper restart ; do not use PD in this clock scheme This value do not provide a proper restart ; do not use PD in this clock scheme PCK Clocking System AT90PWM2/3 OSCCAL DIVIDE ...
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... Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero. • Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL. If PLLF is set, the PLL output is 64Mhz. ...
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... System Clock Prescaler The AT90PWM2/2B/3/3B system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if AT90PWM2/3/2B/ ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 7-12. CLKPS3 4317J–AVR–08/10 Clock Prescaler Select CLKPS2 CLKPS1 AT90PWM2/3/2B/3B CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 39 ...
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... When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Timer/Counters, AT90PWM2/3/2B/3B 40 Table 8-1 presents the different clock systems in the AT90PWM2/2B/3/3B, and their – – ...
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... When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down 4317J–AVR–08/10 , while allowing the other clocks to run. FLASH “Clock Sources” on page AT90PWM2/3/2B/3B , clk , and clk , while allowing I/O CPU FLASH “ ...
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... Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains (1) 1. Only recommended with external crystal or resonator selected as clock source. 2. Only level interrupt PRPSC2 PRPSC1 PRPSC0 PRTIM1 Note:) R/W R/W R/W R PRPSC1 is not used on AT90PWM2/2B Oscillator s Wake-up Sources ( ( ( PRTIM0 PRSPI PRUSART ...
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... ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep 4317J–AVR–08/10 AT90PWM2/3/2B/3B 43 ...
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... If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption. AT90PWM2/3/2B/3B 44 “Analog Comparator” on page 226 for details on the start-up time. “ ...
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... SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in 9.0.2 Reset Sources The AT90PWM2/2B/3/3B has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC AT90PWM2/3/2B/3B 46 Reset Logic Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2 ...
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... MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET Table 9-1) will generate a reset, even if the clock is not running. – on its positive edge, the delay counter starts the MCU after RST – has expired. TOUT External Reset During Operation CC AT90PWM2/3/2B/ RST t TOUT 47 ...
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... Brown-out Detection AT90PWM2/2B/3/3B has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Brown-out Reset During Operation RESET TIME-OUT INTERNAL RESET for details on operation of the Watchdog Timer. Watchdog Reset During Operation – – – AT90PWM2/3/2B/3B V BOT+ BOT- t TOUT – WDRF BORF EXTRF R R/W R/W R/W 0 See Bit Description . Refer to TOUT 0 PORF ...
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... Internal Voltage Reference AT90PWM2/2B/3/3B features an internal bandgap reference (1.1V). This reference is used for Brown-out Detection. a voltage reference for the DAC and/or the ADC, and can also be used as analog input for the analog comparators ...
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... Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. 4317J–AVR–08/10 Watchdog Timer 128 KHz OSCILLATOR WDP3 WDIF WDIE AT90PWM2/3/2B/3B MCU RESET INTERRUPT 51 ...
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... Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. AT90PWM2/3/2B/3B 52 (1) r16, MCUSR r16, (0xff & ...
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... WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included WDIF WDIE WDP3 R/W R/W R AT90PWM2/3/2B/ WDCE WDE WDP2 WDP1 R/W R/W R/W R ...
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... Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 9-6 on page AT90PWM2/3/2B/3B 54 Watchdog Timer Configuration (1) WDE ...
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... WDP2 WDP1 WDP0 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles AT90PWM2/3/2B/3B Typical Time-out at Cycles (2048) cycles 4K (4096) cycles 8K (8192) cycles 0.125 s Reserved = 5. 0.25 s 0.5 s 1.0 s 2.0 s 4 ...
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... Interrupts AT90PWM2/2B/3/3B. For a general explanation of the AVR interrupt handling, refer to and Interrupt Handling” on page 10.1 Interrupt Vectors in AT90PWM2/2B/3/3B Table 10-1. Vector No AT90PWM2/3/2B/3B 56 15. Reset and Interrupt Vectors Program Address Source Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, 0x0000 RESET ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in AT90PWM2/2B/3/3B IVSEL Reset Address 1 ...
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... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM2/2B/3/3B is: Address Labels Code ...
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... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM2/2B/3/3B is: Address Labels Code ...
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... MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); } AT90PWM2/3/2B/ Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” ...
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... Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. 4317J–AVR–08/10 “Electrical Characteristics(1)” on page 298 Pxn C pin AT90PWM2/3/2B/3B and Ground as indicated in Figure CC for a complete list of parameters Logic See Figure " ...
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... The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). AT90PWM2/3/2B/3B 62 (1) Pxn ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 11-2, the PINxn Register bit and the preceding latch con- pd,max AT90PWM2/3/2B/3B Pull-up Comment Default configuration after Reset. No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No ...
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... Figure 11-4. Synchronization when Reading a Software Assigned Pin Value The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin AT90PWM2/3/2B/3B 64 SYSTEM CLK ...
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... Figure 11-2, the digital input signal can be clamped to ground at the input of the “Alternate Port Functions” on page AT90PWM2/3/2B/3B /2. CC 66. 65 ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 11-5. Alternate Port Functions Note: Table 11-2 ure 11-5 in the modules having the alternate function. AT90PWM2/3/2B/3B 66 (1) PUOExn PUOVxn 1 0 ...
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... This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally SPIPS – – PUD R R AT90PWM2/3/2B/ – – IVSEL IVCE MCUCR R R R/W R ...
Page 68
... ADC6/INT2 – Bit 5 ADC6, Analog to Digital Converter, input channel 6 INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU. • APM0+ – Bit 4 AMP0+, Analog Differential Amplifier 0 Positive Input Channel. AT90PWM2/3/2B/3B 68 Port B Pins Alternate Functions Alternate Functions PSCOUT01 output ...
Page 69
... PSCen01 PSCen01 1 SPE • MSTR • SPIPS PSCen11 PSCout01 • SPIPS + PSCout01 • PSCen01 • SPIPS PSCOUT11 + PSCout01 • PSCen01 • SPIPS ADC4D ADC7D 0 0 SCKin • SPIPS • ICP1B ireset ADC4 ADC7 AT90PWM2/3/2B/3B . PB5/ADC6/ INT2 PB4/AMP0 ADC6D + In2en AMP0ND In2en ...
Page 70
... Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 11-6. The alternate pin configuration is as follows: • D2A – Bit 7 D2A, Digital to Analog output • ADC10/ACMP1 – Bit 6 AT90PWM2/3/2B/3B 70 Overriding Signals for Alternate Functions in PB3..PB0 PB3/AMP0- PB2/ADC5/INT1 0 0 ...
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... This pin is also the output pin for the PWM mode timer function. • PSCOUT10/INT3 – Bit 0 PSCOUT10: Output 0 of PSC 1. INT3, External Interrupt source 3: This pin can serve as an external interrupt source to the MCU. 4317J–AVR–08/10 AT90PWM2/3/2B/3B 71 ...
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... DIEOV DI AIO Table 11-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO AT90PWM2/3/2B/3B 72 and Table 11-8 relate the alternate functions of Port C to the overriding signals Figure 11-5 on page 66. Overriding Signals for Alternate Functions in PC7..PC4 PC6/ADC10/ PC7/D2A ACMP1 ...
Page 73
... MOSI_A (Programming & alternate SPI Master Out Slave In) PSCIN2 (PSC 2 Digital Input) OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate Master In SPI Slave Out) PSCIN0 (PSC 0 Digital Input ) CLKO (System Clock Output) PSCOUT00 output XCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select) AT90PWM2/3/2B/3B Table 11-9. 73 ...
Page 74
... CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTD1 and DDD1 settings. It will also be output during reset. • PSCOUT00/XCK/SS_A – Bit 0 PSCOUT00: Output 0 of PSC 0. AT90PWM2/3/2B/3B 74 4317J–AVR–08/10 ...
Page 75
... PD6/ADC3/ ACMP0 ACMPM/INT0 ACMP0D ADC3D + In0en 0 In0en – INT0 ADC3 ACOMP0 ACMPM AT90PWM2/3/2B/3B PD5/ADC2/ PD4/ADC1/RXD/ ACMP2 ICP1A/SCK_A RXEN + SPE • 0 MSTR • SPIPS PD4 • 0 PUD RXEN + SPE • 0 MSTR • SPIPS 0 0 SPE • MSTR • 0 SPIPS 0 – ADC2D ADC1D 0 ...
Page 76
... XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. ADC0, Analog to Digital Converter, input channel 0. • XTAL1/OC0B – Bit 1 AT90PWM2/3/2B/3B 76 PD3/TXD/OC0A/ PD2/PSCIN2/ SS/MOSI_A OC1A/MISO_A TXEN + SPE • ...
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... Port E to the overriding signals shown in 66. PE2/ADC0/ XTAL2 ADC0D 0 Osc Output ADC0 PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R/W AT90PWM2/3/2B/3B PE0/RESET/ PE1/OC0B OCD OC0Ben 0 OC0B Osc / Clock input PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 ...
Page 78
... Initial Value 11.4.8 Port D Data Direction Register – DDRD Bit Read/Write Initial Value 11.4.9 Port D Input Pins Address – PIND Bit Read/Write Initial Value 11.4.10 Port E Data Register – PORTE Bit Read/Write Initial Value AT90PWM2/3/2B/ PINB7 PINB6 PINB5 PINB4 R/W R/W ...
Page 79
... Port E Input Pins Address – PINE Bit Read/Write Initial Value 4317J–AVR–08/ – – – – – – – – AT90PWM2/3/2B/ – DDE2 DDE1 DDE0 R R/W R/W R – PINE2 PINE1 PINE0 R R/W R/W R/W 0 N/A N/A N/A DDRE PINE 79 ...
Page 80
... If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 12-1. ISCn1 AT90PWM2/3/2B/3B 80 28. The I/O clock is halted in all sleep modes except Idle “Electrical Characteristics(1)” on page 28. If the level is sampled twice by the Watchdog Oscillator clock but disappears before ...
Page 81
... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed R/W R/W R R/W R/W R AT90PWM2/3/2B/ INT3 INT2 INT1 R/W R/W R/W R INTF3 INTF2 INTF1 R/W ...
Page 82
... Tn/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. AT90PWM2/3/2B/ Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ) ...
Page 83
... Since the edge detector uses ExtClk clk_I/O clk I/O T0 Synchronization T1 Synchronization clk 1. The synchronization logic on the input pins ( TSM ICPSEL1 – R/W R AT90PWM2/3/2B/3B (1) Clear T1 Tn/T0) is shown in Figure 13- – – – – /2.5. clk_I/O ...
Page 84
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. AT90PWM2/3/2B/3B 84 Table ICPSEL1 ...
Page 85
... Control Logic direction TOP BOTTOM Timer/Counter TCNTn = = 0 = OCRnx Fixed TOP Values = OCRnx TCCRnA TCCRnB AT90PWM2/3/2B/3B Figure 14-1. For the actual 8. CPU accessible I/O Registers, 95. must be written to zero to enable TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCnA (Int.Req.) Waveform OCnA ...
Page 86
... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): AT90PWM2/3/2B/3B 86 Table 14-1 are also used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00 ...
Page 87
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 90. (“Modes of Operation” on page shows a block diagram of the Output Compare unit. AT90PWM2/3/2B/3B in the following. T0 “Modes of 90). 87 ...
Page 88
... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. AT90PWM2/3/2B/3B 88 DATA BUS OCRnx = ...
Page 89
... For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register performed on the next compare match. For compare output actions in the 4317J–AVR–08/10 COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See “8-bit Timer/Counter Register Description” on page 95. AT90PWM2/3/2B/3B Figure 14-4 shows a simplified Q 1 OCnx OCnx Pin DDR 89 ...
Page 90
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. AT90PWM2/3/2B/3B 90 Table 14-2 on page 96. For fast PWM mode, refer to Table 14-4 on page 89.). “ ...
Page 91
... PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and 4317J–AVR–08/ clk_I ------------------------------------------------- - OCnx ⋅ ⋅ OCRnx 1 + Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- AT90PWM2/3/2B/3B OCnx Interrupt Flag Set (COMnx1 OC0 ) = 91 ...
Page 92
... OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. AT90PWM2/3/2B/ ...
Page 93
... TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare 4317J–AVR–08/10 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 Table 14-7 on page AT90PWM2/3/2B/3B OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 94
... MAX value in all modes other than phase correct PWM mode. Figure 14-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk I/O TCNTn TOVn Figure 14-9 AT90PWM2/3/2B/ OCnxPCPWM Figure 14-7 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) MAX - 1 shows the same timing data, but with the prescaler enabled ...
Page 95
... OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - COM0A1 COM0A0 COM0B1 R/W R/W R AT90PWM2/3/2B/3B /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP COM0B0 – – WGM01 R R/W ...
Page 96
... Table 14-4 rect PWM mode. Table 14-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode AT90PWM2/3/2B/3B 96 Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. 1 ...
Page 97
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode 4317J–AVR–08/10 Table 14-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits ...
Page 98
... TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a AT90PWM2/3/2B/3B 98 Table 14-8. Modes of operation supported by the Timer/Counter ...
Page 99
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 100
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 101
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 4317J–AVR–08/10 AT90PWM2/3/2B/3B Table 98. 14-8, “Waveform ...
Page 102
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM1 bit in Timer/Counter1 module. AT90PWM2/3/2B/3B 102 “Pin Descriptions” on page “16-bit Timer/Counter Register Description” on page “Power Reduction Register” on page 42 Figure 15-1 ...
Page 103
... Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Table on page 4 1. Refer to for Timer/Counter1 pin placement and description. The compare match event will also set the Compare Match Flag (OCFnx) AT90PWM2/3/2B/3B (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = ...
Page 104
... The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. AT90PWM2/3/2B/3B 104 The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). ...
Page 105
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM2/3/2B/3B 105 ...
Page 106
... SREG = sreg; return i; } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. AT90PWM2/3/2B/3B 106 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...
Page 107
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. “Timer/Counter0 and Timer/Counter1 Prescalers” on page AT90PWM2/3/2B/3B 82. 107 ...
Page 108
... Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. AT90PWM2/3/2B/3B 108 shows a block diagram of the counter and its surroundings. DATA BUS ...
Page 109
... ICRnL. 4317J–AVR–08/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ICPSEL1 ICPnA ICPnB AT90PWM2/3/2B/3B Figure 15-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int ...
Page 110
... Compare Flag (OCFnx) at the next “timer clock cycle”. If enabled (OCIEnx = 1), the Output Com- pare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ- AT90PWM2/3/2B/3B 110 104. 82). The edge detector is also identical. However, when the noise canceler is “ ...
Page 111
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM AT90PWM2/3/2B/3B 102.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 112
... PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin system reset occur, the OCnx Register is reset to “0”. AT90PWM2/3/2B/3B 112 104. “Accessing 16-bit Registers” ...
Page 113
... Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, 4317J–AVR–08/10 Waveform Generator I/O See “16-bit Timer/Counter Register Description” on page 122. Table 15-2 on page AT90PWM2/3/2B/ OCnx ...
Page 114
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period AT90PWM2/3/2B/3B 114 112.) “Timer/Counter Timing Diagrams” on page Figure 121 ...
Page 115
... OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 4317J–AVR–08/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ FPWM AT90PWM2/3/2B/3B f clk_I/O ⋅ OCRnA TOP log + 1 ---------------------------------- - log Figure 15-7 ...
Page 116
... The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). AT90PWM2/3/2B/3B 116 1 2 ...
Page 117
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter- rupt Flag will be set when a compare match occurs. 4317J–AVR–08/10 AT90PWM2/3/2B/3B f clk_I ...
Page 118
... OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis- ter at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when AT90PWM2/3/2B/3B 118 1 2 ...
Page 119
... PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs. 4317J–AVR–08/10 f OCnxPCPWM 15-9 PFCPWM Figure 15-9. The figure shows phase and frequency correct AT90PWM2/3/2B/3B f clk_I/O = --------------------------- - ⋅ ⋅ TOP ( ) TOP log ...
Page 120
... OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). AT90PWM2/3/2B/3B 120 1 2 ...
Page 121
... I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the count sequence close to TOP in various modes. When using phase and AT90PWM2/3/2B/ therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) ...
Page 122
... If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the AT90PWM2/3/2B/3B 122 clk ...
Page 123
... COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) PWM COMnA0/COMnB0 0 0 AT90PWM2/3/2B/3B shows the COMnx1:0 bit functionality when the Description Normal port operation, OCnA/OCnB disconnected. Toggle OCnA/OCnB on Compare Match. Clear OCnA/OCnB on Compare Match (Set output to low level). ...
Page 124
... AT90PWM2/3/2B/3B 124 Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) PWM COMnA0/COMnB0 special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. “Phase Correct PWM Mode” on page 117. Table 15-5. Modes of operation supported by the Timer/Counter (1) WGMn0 Timer/Counter Mode of ...
Page 125
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge. AT90PWM2/3/2B/3B WGM n2:0 definitions. However, the functionality and WGM12 CS12 CS11 R/W R/W R CS10 ...
Page 126
... Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. 15.10.5 Output Compare Register 1 A – OCR1AH and OCR1AL Bit Read/Write Initial Value 15.10.6 Output Compare Register 1 B – OCR1BH and OCR1BL Bit AT90PWM2/3/2B/3B 126 FOC1A FOC1B – – ...
Page 127
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 128
... ICF1 can be cleared by writing a logic one to its bit location. • Bit 4, 3 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero. • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B) ...
Page 129
... Zero crossing retriggering • Demagnetization retriggering • Fault input The PSC can be chained and synchronized to provide a configuration to drive three half bridges. Thanks to this feature it is possible to generate a three phase waveforms for applications such as Asynchronous or BLDC motor drive. 4317J–AVR–08/10 AT90PWM2/3/2B/3B 129 ...
Page 130
... The PSC is seen as two symetrical entities. One part named part A which generates the output PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output. Each part has its own PSC Input Module to manage selected input. AT90PWM2/3/2B/3B 130 PSC Counter ...
Page 131
... Part A = PSC Input Module A OCRnRA Waveform = Generator A OCRnSA Part B PICRn PCNFn PFRCnB PCTLn PFRCnA (See “Output Matrix” on page AT90PWM2/3/2B/3B PSCOUTn3 POS23 PSCOUTn1 ( From Analog Comparator n Ouput ) PSCn Input B Output PISELnB Matrix PSCn Input A PSCINn PISELnA PSCOUTn2 POS22 PSCOUTn0 POM2(PSC2 only) PSOCn 157 ...
Page 132
... Signal Description Figure 16-3. PSC External Block View Note: 16.4.1 Input Description Table 16-1. Name OCRnRB[1 1:0] OCRnSB[1 1:0] OCRnRA[1 1:0] OCRnSA[1 1:0] AT90PWM2/3/2B/3B 132 CLK PLL CLK I/O SYnIn StopOut 12 OCRnRB[11:0] 12 OCRnSB[11:0] 12 OCRnRA[11:0] 12 OCRnSA[11:0] 4 OCRnRB[15:12] (Flank Width Modulation) 12 PICRn[11:0] ...
Page 133
... Counter value at retriggering event PSC Interrupt Request : three souces, overflow, fault, and input capture ADC Synchronization (+ Amplifier Syncho. ) Stop Output (for synchronized mode) 1. See Figure 16-38 on page 158 2. See “Analog Synchronization” on page 157. AT90PWM2/3/2B/3B Type Width Register 4 bits Signal Signal (1) Signal ...
Page 134
... Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down. Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp. AT90PWM2/3/2B/3B 134 PSC Cycle Sub-Cycle A ...
Page 135
... One moment for PSCn1 description with OT1 which gives the time of the whole moment 4317J–AVR–08/10 Four Ramp mode Two Ramp mode One Ramp mode Center Aligned mode OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 and Dead-Time 1/Fclkpsc AT90PWM2/3/2B/3B OCRnRB OCRnSB 0 On-Time 1 Dead-Time 1 135 ...
Page 136
... Dead-Time 1 values with : On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH 1/Fclkpsc Note: 16.5.2.3 One Ramp Mode In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other. AT90PWM2/3/2B/3B 136 OCRnRA OCRnSA OCRnSB 0 0 On-Time 0 Dead-Time 0 ...
Page 137
... Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: 16.5.2.4 Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered. 4317J–AVR–08/10 OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 = 1/Fclkpsc AT90PWM2/3/2B/3B OCRnRB OCRnSB On-Time 1 Dead-Time 1 137 ...
Page 138
... PSC Counter OCRnRB OCRnSB OCRnSA 0 On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 (AT90PWM2/3) PSCOUTn1 (AT90PWM2B/3B) Dead-Time PSC Cycle Minimal value for PSC Cycle = 2 * 1/Fclkpsc See “Analog Synchronization” on page 157. See “PSC 0 Control Register – PCTL0” on page On-Time 1 Dead-Time ). 0 164.(or PCTL1 or PCTL2) 4317J–AVR–08/10 ...
Page 139
... Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the 4317J–AVR–08/10 Regulation Loop Writting in Calculation PSC Registers Cycle Cycle Cycle Cycle With Set i With Set i With Set i With Set i page AT90PWM2/3/2B/3B Request for an Update Cycle With Set j End of Cycle 162. 139 ...
Page 140
... In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu- tive cycles. f and f b1 Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz. AT90PWM2/3/2B/3B 140 Δ – = period in a PSC cycle and is given by the following formula: PSC is the output operating frequency ...
Page 141
... Figure 16-12. Resulting Frequency versus 4317J–AVR–08/10 and f where the nearest base frequency below the wanted frequency. The number Distribution the modulated frame b2 PWM - cycle prime cycle corresponding cycle AT90PWM2/3/2B/3B is the nearest base frequency above the wanted The f and f frequencies are evenly distrib ...
Page 142
... Figure 16-13. Enhanced Mode, Timing Diagram DT0 OT0 PSCOUTn0 PSCOUTn1 Period The supplementary step in counting to generate f in the frame according to the fractional divider. lated frame,” on page The waveform frequency is defined by the following equations the fractionel divider factor. AT90PWM2/3/2B/3B 142 ----------------------------- - = ---------------------------------------------------------------------- PSCn ( PSCnCycle ...
Page 143
... Digital 1 Filter 1 PFLTEnA CLK PSC (PFLTEnB) PISELnA (PISELnB) PELEVnA / PCAEnA 2 (PELEVnB) (PCAEnB) 4 PRFMnA3:0 (PRFMnB3:0) CLK PSC CLK PSC AT90PWM2/3/2B/3B 16.25.14page 167), PSCnIN0/1 input can act Input Processing (retriggering ...) PSC Core Output (Counter, Control PSCOUTn0 Waveform (PSCOUTn1) Generator, ...) (PSCOUT22) (PSCOUT23) 143 ...
Page 144
... The polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the analog comparator or the PSCINn input. As the period of the cycle decreases, the instantaneous frequency of the two outputs increases. AT90PWM2/3/2B/3B 144 On-Time 0 Dead-Time 0 Dead-Time 1 This exemple is given in “ ...
Page 145
... This exemple is given in “Input Mode 1” in “ ramp mode” See Figure 16-20. for details. On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Mode 4 ( See Figure 16-24. and Figure 16-25. for details.) AT90PWM2/3/2B/3B On-Time 1 Dead-Time 0 On-Time 1 Dead-Time 1 ...
Page 146
... Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section “PSC n Input A Control Register – PFRCnA”, page 16716.25.14. AT90PWM2/3/2B/3B 146 OFF BURST is running. So thanks to PSC Asynchronous Output Control bit ...
Page 147
... See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page 1001b 153. Reserved : Do not use 1010b 1011b 1100b 1101b See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and 1110b Disactivate Output” on page 154. Reserved : Do not use 1111b AT90PWM2/3/2B/3B 147 ...
Page 148
... PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0. When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state and then jumps and executes DT0 plus OT0. AT90PWM2/3/2B/3B 148 DT0 ...
Page 149
... PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 4317J–AVR–08/10 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM2/3/2B/3B DT0 OT0 DT1 DT0 OT0 DT1 OT1 OT1 149 ...
Page 150
... When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0 plus DT1 while PSC Input active state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 16.12 PSC Input Mode 4: Deactivate outputs without changing timing. AT90PWM2/3/2B/3B 150 DT0 OT0 DT1 DT1 OT1 ...
Page 151
... Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 4317J–AVR–08/10 DT1 OT1 DT0 OT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 AT90PWM2/3/2B/3B DT1 OT1 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 DT0 OT0 DT1 OT1 ...
Page 152
... PSCOUTn1 PSCn Input A or PSCn Input B Note: Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 16.16 PSC Input Mode 8: Edge Retrigger PSC AT90PWM2/3/2B/3B 152 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 1. Software action is the setting of the PRUNn bit in PCTLn register. ...
Page 153
... Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC doesn’t jump to the opposite dead-time. 16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 4317J–AVR–08/10 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT1 OT1 OT1 AT90PWM2/3/2B/3B DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 153 ...
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... Figure 16-34. PSC behaviour versus PSCn Input B in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input B The retrigger event is taken into account only if it occurs during the corresponding On-Time. 16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output AT90PWM2/3/2B/3B 154 DT0 OT0 DT1 DT1 OT1 DT0 ...
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... Retrigger/Fault input is actve. The PSC runs at con- stant frequency. AT90PWM2/3 : The retrigger event is taken into account only if it occurs during the correspond- ing On-Time. In the case of the retrigger event is not taken into account, the following active outputs remains active, they are not desactivated. 4317J– ...
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... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. AT90PWM2/3/2B/3B 156 Available Input Modes according to Running Modes 1 Ramp Mode ...
Page 157
... Analog Synchronization PSC generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. 4317J–AVR–08/10 Output Matrix versus ramp number Ramp 0 Ramp 1 POMV2A0 POMV2A1 POMV2B0 POMV2B1 Output Matrix AT90PWM2/3/2B/3B Ramp 2 Ramp 3 POMV2A2 POMV2A3 POMV2B2 POMV2B3 PSCOUT20 0 PSCOUT22 1 POS22 POS23 ...
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... If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1. PRUNn and PARUNn bits are located in PCTLn register. on page 164. See “PSC 1 Control Register – PCTL1” on page 165. See “PSC 2 Control Register – PCTL2” on page 166. AT90PWM2/3/2B/3B 158 SY0In Run PSC0 ...
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... PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source. PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock. 4317J–AVR–08/10 1 PLL CK 0 I/O PCLKSELn (1) : CK/16 for AT90PWM2/3 (2) : CK/64 for AT90PWM2/3 AT90PWM2/3/2B/3B PRESCALER PPREn1/0 CLK PSCn 159 ...
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... PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs • PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger, capture of the PSC counter or Synchro Error. 16.26.216.26.2See PSCn Interrupt Mask Register page 171. 16.24.2 PSC Interrupt Vectors in AT90PWM2/2B/3/3B Table 16-10. PSC Interrupt Vectors Vector No ...
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... Send signal on leading edge of PSCOUTn0 (match with OCRnSA) Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or 1 fault/retrigger on part A) 0 Send signal on leading edge of PSCOUTn1 (match with OCRnSB) Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or 1 fault/retrigger on part B) AT90PWM2/3/2B/ POEN0B - POEN0A ...
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... Output Compare RA Register – OCRnRAH and OCRnRAL Bit Read/Write Initial Value 16.25.6 Output Compare SB Register – OCRnSBH and OCRnSBL Bit AT90PWM2/3/2B/3B 162 PSYNCn0 Description Send signal on match with OCRnRA (during counting down of PSC). The 0 min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The 1 min value of OCRnRA must be 1 ...
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... OCRnRB[15:12] OCRnRB[7: PFIFTY0 PALOCK0 PLOCK0 PMODE01 R/W R/W R/W R PFIFTY1 PALOCK1 PLOCK1 PMODE11 R/W R/W R/W R PFIFTY2 PALOCK2 PLOCK2 PMODE21 R/W R/W R/W R AT90PWM2/3/2B/ OCRnRB[11: PMODE00 POP0 PCLKSEL0 - R/W R/W R/W R PMODE10 POP1 PCLKSEL1 - R/W R/W R/W R PMODE20 POP2 PCLKSEL2 ...
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... Set this bit to enable the Output Matrix feature on PSC2 outputs. See 157. When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs. 16.25.11 PSC 0 Control Register – PCTL0 Bit Read/Write Initial Value AT90PWM2/3/2B/3B 164 PMODEn0 Description 0 One Ramp Mode 1 ...
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... Divide the PSC clock PPRE11 PPRE10 PBFM1 PAOC1B R/W R/W R/W R AT90PWM2/3/2B/3B Description PWM2B/3B No divider on PSC input clock Divide the PSC input clock by 4 Divide the PSC input clock by 32 Divide the PSC clock by 256 PAOC1A PARUN1 PCCYC1 PRUN1 R/W R/W R/W ...
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... Bit 0 – PRUN1 : PSC 1 Run Writing this bit to one starts the PSC 1. When set, this bit prevails over PARUN1 bit. 16.25.13 PSC 2 Control Register – PCTL2 Bit Read/Write Initial Value AT90PWM2/3/2B/3B 166 PPRE10 Description PWM2 divider on PSC input clock 1 Divide the PSC input clock by 4 ...
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... Divide the PSC clock PCAEnA PISELnA PELEVnA PFLTEnA R/W R/W R/W R AT90PWM2/3/2B/3B Description PWM2B/3B No divider on PSC input clock Divide the PSC input clock by 4 Divide the PSC input clock by 32 Divide the PSC clock by 256 PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 R/W R/W R/W R ...
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... These four bits define the mode of operation of the Fault or Retrigger functions. (see PSC Functional Specification for more explanations) Table 16-17. Level Sensitivity and Fault Mode Operation PRFMnx3:0 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b AT90PWM2/3/2B/3B 168 PCAEnB PISELnB PELEVnB PFLTEnB R/W R/W R/W ...
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... CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers. Note for AT90PWM2/3 : This register is read only and a write to this register is not allowed. 4317J–AVR–08/10 Description ...
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... This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0 16.26.2 PSC0 Interrupt Mask Register – PIM0 Bit Read/Write Initial Value 16.26.3 PSC1 Interrupt Mask Register – PIM1 Bit Read/Write Initial Value AT90PWM2/3/2B/3B 170 POMV2B3 POMV2B2 POMV2B1 POMV2B0 R/W R/W ...
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... Bit Read/Write Initial Value • Bit 7 – POACnB : PSC n Output B Activity (not implemented on AT90PWM2/3) This bit is set by hardware each time the output PSCOUTn1 changes from from Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn’t change due to a freezen external input signal. • ...
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... Bit 0 – PEOPn: End Of PSC n Interrupt This bit is set by hardware when PSC n achieves its whole cycle. Must be cleared by software by writing a one to its location. AT90PWM2/3/2B/3B 172 PRNn0 Description 0 The last event which has generated an interrupt occured during ramp 1 1 The last event which has generated an interrupt occured during ramp 2 ...
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... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM2/2B/3/3B and peripheral devices or between several AVR devices. The AT90PWM2/2B/3/3B SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 174
... SPI clock should never exceed f When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 17-1. Pin MOSI AT90PWM2/3/2B/3B 174 Table 17-1. For more details on automatic port overrides, refer to 66. (1) SPI Pin Overrides ...
Page 175
... SPI Pin Overrides Direction, Master SPI Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 68 direction of the user defined SPI pins. AT90PWM2/3/2B/3B Direction, Slave SPI User Defined Input Input for a detailed description of how to define the 175 ...
Page 176
... Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. AT90PWM2/3/2B/3B 176 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ...
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... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. The example code assumes that the part specific header file is included. AT90PWM2/3/2B/3B 177 ...
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... On 32 pins packages, SPIPS has the following action: – – pins package, SPIPS has the following action: – – Note that programming port are always located on alternate SPI port. 17.2.4 SPI Control Register – SPCR Bit AT90PWM2/3/2B/3B 178 SPIPS – – R/W R ...
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... Figure 17-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 17-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup AT90PWM2/3/2B/3B R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 17-4 for an example. The CPOL Trailing Edge ...
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... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
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... SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 AT90PWM2/3/2B/3B Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 182
... Figure 17-4. SPI Transfer Format with CPHA = 1 AT90PWM2/3/2B/3B 182 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 ...
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... Bit ordering configuration (MSB or LSB first) – Sleep mode exit under reception of EUSART frame 18.2 Overview A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. 4317J–AVR–08/10 AT90PWM2/3/2B/3B Figure 18-1. CPU accessible 183 ...
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... Frame Error, Data OverRun and Parity Errors. 18.3 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- AT90PWM2/3/2B/3B 184 (1) UBRR[H:L] BAUD RATE GENERATOR ...
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... UBRRn f clk UBRRn+1 Prescaling Down-Counter clk io Sync Register Detector xn cki XCKn xn cko Pin DDR_XCKn UCPOLn operation. System I/O Clock frequency. AT90PWM2/3/2B/ DDR_XCKn Edge Figure 18-2. f clk /(UBRR+1)). The Transmitter divides the io U2Xn txn clk 1 0 ...
Page 186
... Transmitter and Receiver. This process intro- duces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: AT90PWM2/3/2B/3B 186 contains equations for calculating the baud rate (in bits per second) and for calculat- ...
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... It is therefore recommended io UCPOLn = 1 XCKn RxDn / TxDn UCPOLn = 0 XCKn RxDn / TxDn Figure 18-3 shows, when UCPOL is zero the data will be changed at illustrates the possible combinations of the frame formats. Bits inside brackets are AT90PWM2/3/2B/3B Sample Sample 187 ...
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... Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC flag can be used to check that the Transmitter has completed all transfers, and the RXC flag can be used to check AT90PWM2/3/2B/3B 188 (IDLE) ...
Page 189
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM2/3/2B/3B 189 ...
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... If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. AT90PWM2/3/2B/3B 190 (1) (1) ...
Page 191
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM2/3/2B/3B 191 ...
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... The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used. AT90PWM2/3/2B/3B 192 4317J–AVR–08/10 ...
Page 193
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM2/3/2B/3B 193 ...
Page 194
... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE0)|(1<<DOR0)|(1<<UPE0 Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: AT90PWM2/3/2B/3B 194 (1) r18, UCSRA r17, HIGH(-1) r16, LOW(-1) r17 (1) ; return -1; ...
Page 195
... CH1 and CH2, CH3 is lost. When a Data OverRun condition is detected, the OverRun error is memorized. When the two characters CH1 and CH2 are read from the receive buffer, the DOR bit is set (and not before) and RxC remains set to warn the application about the overrun error. 4317J–AVR–08/10 AT90PWM2/3/2B/3B 195 ...
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... Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. AT90PWM2/3/2B/3B 196 CH1 CH2 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. RxDn IDLE Sample (U2Xn = Sample (U2Xn = AT90PWM2/3/2B/3B START Figure 18-6 ...
Page 198
... For Normal Speed mode, the first low level sample can be at point marked (A) in (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver. AT90PWM2/3/2B/3B 198 RxDn Sample ...
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... Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (%) R slow fast 5 93.20 106.67 6 94.12 105.79 7 94.81 105.11 8 95.36 104.58 9 95.81 104.14 10 96.17 103.78 AT90PWM2/3/2B/ ----------------------------------- fast ( ) for normal speed and for normal speed and M Recommended Max (%) Max Total Error (%) Receiver Error (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4 ...
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... Using MPCM For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame AT90PWM2/3/2B/3B 200 Recommended Maximum Receiver Baud Rate Error for Double Speed Mode ...